Micrel, Inc.
KSZ9021RL/RN
Auto-Negotiation Interval Timers
Transmit Burst interval
Time Duration
16 ms
Transmit Pulse interval
68 us
FLP detect minimum time
FLP detect maximum time
Receive minimum Burst interval
Receive maximum Burst interval
Data detect minimum interval
Data detect maximum interval
NLP test minimum interval
NLP test maximum interval
Link Loss time
17.2 us
185 us
6.8 ms
112 ms
35.4 us
95 us
4.5 ms
30 ms
52 ms
Break Link time
1480 ms
830 ms
1000 ms
Parallel Detection wait time
Link Enable wait time
Table 2. Auto-Negotiation Timers
RGMII Interface
The Reduced Gigabit Media Independent Interface (RGMII) is compliant with the RGMII Version 1.3 Specification. It
provides a common interface between RGMII PHYs and MACs, and has the following key characteristics:
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•
•
•
Pin count is reduced from 24 pins for the IEEE Gigabit Media Independent Interface (GMII) to 12 pins for RGMII.
All speeds (10Mbps, 100Mbps, and 1000Mbps) are supported at both half and full duplex.
Data transmission and reception are independent and belong to separate signal groups.
Transmit data and receive data are each 4-bit wide, a nibble.
In RGMII operation, the RGMII pins function as follow:
•
•
•
•
The MAC sources the transmit reference clock, TXC, at 125MHz for 1000Mbps, 25MHz for 100Mbps and 2.5MHz
for 10Mbps.
The PHY recovers and sources the receive reference clock, RXC, at 125MHz for 1000Mbps, 25MHz for 100Mbps
and 2.5MHz for 10Mbps.
For 1000Base-T, the transmit data, TXD[3:0], is presented on both edges of TXC, and the received data,
RXD[3:0], is clocked out on both edges of the recovered 125 MHz clock, RXC.
For 10Base-T/100Base-TX, the MAC will hold TX_CTL low until both PHY and MAC operate at the same speed.
During the speed transition, the receive clock will be stretched on either positive or negative pulse to ensure that
no clock glitch is presented to the MAC at any time.
•
TX_ER and RX_ER are combined with TX_EN and RX_DV, respectively, to form TX_CTL and RX_CTL. These
two RGMII control signals are valid at the falling clock edge.
After power-up or reset, the KSZ9021RL/RN is configured to RGMII mode if the MODE[3:0] strap-in pins are set to one of
the RGMII mode capability options. See Strapping Options section for available options.
The KSZ9021RL/RN has the option to output a low jitter 125MHz reference clock on the CLK125_NDO pin. This clock
provides a lower cost reference clock alternative for RGMII MACs that require a 125MHz crystal or oscillator. The 125MHz
clock output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high.
M9999-101309-1.1
October 2009
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MICREL [ MICREL SEMICONDUCTOR ]
