W78M32VP-XBX
TABLE 40 – SECTOR PROTECTION COMMAND DEFINITIONS
Command
Bus Cycles (Note 1-5)
First
Second
Third
Fouth
Fifth
Sixth
Addr
555
XXX
00
Data
AA
Addr
2AA
XXX
Data
55
Addr
555
Data
Addr
Data
Addr
Data
Addr
Data
Command Set Entry
Program (6)
3
2
1
2
3
2
4
A0
DATA
Read (6)
RD
90
Command Set Exit (7, 8)
Command Set Entry
Password Program (9)
Password Read (10)
XXX
555
XXX
00
XXX
2AA
PWAx
01
00
55
AA
555
A0
PWDx
PWD 1
03
PWD0
25
02
00
PWD 2
PWD 0
03
01
PWD 3
PWD 1
00
00
02
PWD 2
03
PWD 3
Password Unlock (10)
7
00
29
Command Set Exit (7, 8)
PPB Command Set Entry
PPB Program (11, 12)
2
3
2
2
1
2
3
2
1
2
3
2
2
1
2
XXX
555
XXX
XXX
SA
90
XXX
2AA
SA
00
55
00
30
AA
555
A0
All PPB Erase (13)
80
00
PPB Status Read (12)
RD (0)
90
PPB Command Set Exit (7, 8)
PPB Lock Cammand Set Entry
PPB Lock Set (12)
XXX
555
XXX
XXX
XXX
555
XXX
XXX
SA
XXX
2AA
XXX
00
55
00
AA
555
555
A0
PPB Lock Command Set Exit (7, 8)
PPB Lock Command Set Exit (7, 8)
DYB Command Set Entry
DYB Set (11, 12)
RD (0)
90
XXX
2AA
SA
00
55
00
01
AA
A0
DYB Clear (12)
A0
SA
DYB Status Read (12)
RD (0)
90
DYB Command Set Exit (7, 8)
XXX
XXX
00
Legend
X = Don’t care
RD(0) = Read data.
SA = Sector Address. Address bits Amax–A16 uniquely select any sector.
PWD = Password
PWDx = Password word0, word1, word2, and word3.
Data = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit,
PD(1) = Persistent Protection Mode Lock Bit, PD(2) = Password Protection Mode Lock Bit.
Notes
1. See Table 7.1 for description of bus operations.
2. All values are in hexadecimal.
3. All bus cycles are write cycles unless otherwise noted.
4. Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.
5. Address bits AMAX:A16 are don’t cares for unlock and command cycles, unless SA or PA
required. (AMAX is the Highest Address pin.)
7. The Exit command returns the device to reading the array.
8. If any Command Set Entry command was written, an Exit command must be issued to reset the
device into read mode.
9. For PWDx, only one portion of the password can be programmed per each “A0” command.
10. Note that the password portion can be entered or read in any order as long as the entire 64-bit
password is entered or read.
6. All Lock Register bits are one-time programmable. Program state = “0” and the erase state = “1.”
The Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be
programmed at the same time or the Lock Register Bits Program operation aborts and returns
the device to read mode. Lock Register bits that are reserved for future use default to “1’s.” The
Lock Register is shipped out as “FFFF’s” before Lock Register Bit program execution.
11. If ACC = VHH, sector protection matches when ACC = VIH.
12. Protected State = “00h,” Unprotected State = “01h.”
13. The All PPB Erase command embeds programming of all PPB bits before erasure.
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 15
26
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