W3H32M64EA-XSBX
ADVANCED
FIGURE 4 – POWER-UP AND INITIALIZATION
VCC
VCC
L
V
CC
Q
1
1
tVTD
V
tt
Vref
Tk0
Tl0
Tm0
Tg0
Th0
Ti0
Tj0
Te0
Tf0
Tc0
Td0
Tb0
T0
Ta0
t
CK
CK#
CK
t
t
CL
CL
LVCMOS
SSTL_18
2
2
CKE
ODT
low level
low level
3
5
6
7
8
9
10
REF
10
REF
11
12
13
14
Valid
Command
NOP
PRE
LM
LM
LM
LM
PRE
LM
LM
LM
15
DM
16
Address
Code
Code
Code
A10 = 1
Code
Code
Code
Code
A10 = 1
Valid
15
High-Z
High-Z
High-Z
DQS
15
DQ
R
tt
4
3
t
t
t
t
t
t
t
t
t
MRD
t
T = 400ns (MIN)
t
T = 200μs (MIN)
RPA
MRD
MRD
MRD
MRD
RPA
RFC
RFC
MRD
MRD
See no te 10
Power-up:
EMR(2)
EMR(3)
EMR
V
and stable
cldodck (CK, CK#)
MR without
EMR with
EMR with
OCD exit
DLL RESET OCD default
200 cycles of CK are required before a READ command can be issued
Normal
operation
MR with
DLL RESET
Indicates a Break in
Time Scale
Don’t care
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev.1
7
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