W3H128M72E-XSBX / W3H128M72E-XNBX
FIGURE 4 – POWER-UP AND INITIALIZATION
VCC
VCCL
VCCQ
1
tVTD
1
VTT
VREF
Tk0
Tl0
Tm0
Tg0
Th0
Ti0
Tj0
Te0
Tf0
Tb0
Tc0
Td0
T0
Ta0
tCK
CK#
CK
tCL
tCL
LVCMOS
SSTL_18
low level2
CKE low level2
ODT
LM11
LM12
LM13
Valid14
LM5
LM6
LM7
LM8
PRE9
REF10
REF10
NOP3
Command
PRE
DM15
Address16
Code
Code
Code
A10 = 1
Code
Code
Code
Code
A10 = 1
Valid
High-Z
DQS15
DQ15
High-Z
High-Z
RTT
T = 400ns (MIN)4
T = 200μs (MIN)3
tRPA
tMRD
tMRD
tMRD
tMRD
tRPA
tRFC
tRFC
tMRD
tMRD
tMRD
See note 10
Power-up:
VCC and stable
clock (CK, CK#)
EMR(2)
EMR(3)
EMR
MR without
EMR with
EMR with
OCD exit
DLL RESET OCD default
Indicates a Break in
Time Scale
200 cycles of CK are required before a READ command can be issued
Don’t care
Normal
operation
MR with
DLL RESET
NOTES:
1. Applying power; if CKE is maintained below 0.2 x VCCQ, outputs remain disabled. To guarantee
TT (ODT resistance) is off, VREF must be valid and a low level must be applied to the ODT ball
4. Wait a minimum of 400ns then issue a PRECHARGE ALL command.
5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2) command, provide LOW
to BA0, and provide HIGH to BA1; set register E7 to “0” or “1” to select appropriate self refresh
rate; remaining EMR(2) bits must be “0” (see Extended Mode Register 2 (EMR2) for all EMR(2)
requirements).
R
(all other inputs may be undefined, I/Os and outputs must be less than VCCQ during voltage ramp
time to avoid DDR2 SDRAM device latch-up). At least one of the following two sets of conditions
(A or B) must be met to obtain a stable supply state (stable supply defined as VCC, VCCQ,VREF
,
and VTT are between their minimum and maximum values as stated in DC Operating Conditions
table):
A. (single power source) The VCC voltage ramp from 300mV to VCC (MIN) must take no longer
than 200ms; during the VCC voltage ramp, |VCC - VCCQ| ≤ 0.3V. Once supply voltage ramping
is complete (when VCCQ crosses VCC (MIN), DC Operating Conditions table specifications
apply.
6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3) command, provide HIGH
to BA0 and BA1; remaining EMR(3) bits must be “0.” Extended Mode Register 3 (EMR3) for all
EMR(3) requirements.
7. Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE command,
provide LOW to BA1 and A0; provide HIGH to BA0; bits E7, E8, and E9 can be set to “0” or
“1;” It is recommended setting them to “0;” remaining EMR bits must be “0.” Extended Mode
Register (EMR) for all EMR requirements.
8. Issue a LOAD MODE command to the MR for DLL RESET. 200 cycles of clock input is required
to lock the DLL. To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA1 and BA0;
CKE must be HIGH the entire time the DLL is resetting; remaining MR bits must be “0.” Mode
Register (MR) for all MR requirements.
•
•
•
V
V
V
CC, VCCQ are driven from a single power converter output
TT is limited to 0.95V MAX
REF tracks VCCQ/2; VREF must be within ±0.3V with respect to VCCQ/2 during supply ramp
time.
VCCQ ≥ VREF at all times
•
B. (multiple power sources) VCC ≥ VCCQ must be maintained during supply voltage ramping,
9. Issue PRECHARGE ALL command.
for both AC and DC levels, until supply voltage ramping completes (VCCQ crosses
10. Issue two or more REFRESH commands.
V
CC [MIN]). Once supply voltage ramping is complete, DC Operating Conditions table
11. Issue a LOAD MODE command to the MR with LOW to A8 to initialize device operation (that
is, to program operating parameters without resetting the DLL). To access the MR, set BA0 and
BA1 LOW; remaining MR bits must be set to desired settings. Mode Register (MR) for all MR
requirements.
12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and
E9 to “1,” and then setting all other desired parameters. To access the EMR, set BA0 HIGH and
BA1 LOW (see Extended Mode Register (EMR) for all EMR requirements.
13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9 to
“0,” and then setting all other desired parameters. To access the extended mode registers, EMR,
set BA0 HIGH and BA1 LOW for all EMR requirements.
14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after the
DLL RESET at Tf0.
15. DM represents UDM and LDM; DQS represents UDQS, UDQS#, LDQS and LDQS#. DQ
represents DQ[71:0].
16. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are
required to be decoded).
specifications apply.
•
•
Apply VCC before or at the same time as VCCQ; VCC voltage ramp time must be ≤ 200ms
from when VCC ramps from 300mV to VCC (MIN)
Apply VCCQ before or at the same time as VTT; the VCCQ voltage ramp time from when
VCC (MIN) is achieved to when VCCQ (MIN) is achieved must be ≤ 500ms; while VCC is
ramping, current can be supplied from VCC through the device to VCCQ
VREF must track VCCQ/2, VREF must be within ±0.3V with respect to VCCQ/2 during supply
ramp time; VCCQ ≥ VREF must be met at all times
Apply VTT; The VTT voltage ramp time from when VCCQ (MIN) is achieved to when VTT (MIN)
is achieved must be no greater than 500ms
•
•
2. CKE uses LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device power-
up prior to VREF. being stable. After state T0, CKE is required to have SSTL_18 input levels.
Once CKE transitions to a high level, it must stay HIGH for the duration on the initialization
sequence.
3. For a minimum of 200μs after stable power and clock (CK, CK#), apply NOP or DESELECT
commands, then take CKE HIGH.
6
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
