MDT10F630
(17).
(18).
11 ~ 18H : Unimplemented register.
19H : Comparator control register.
Bit 7
-
Bit 6
Bit 5
-
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMSTA
CMOUT
CMOINV
CMIS
CMP2
CMP1
CMP0
CMOUT : Comparator Output Bit.
When CMOINV = 0
1 = Vin+ > Vin- ; 0 = Vin+ < Vin-
When CMOINV = 1
1 = Vin+< Vin- ; 0 = Vin+ > Vin-
CMOINV: Comparator Output Inversion Bit.
0 = Output not inverted
1 = Output inverted
CMIS: Comparator Input Switch Bit.
When CMP2 ~ 0 = 110 or 101 :
0 = Vin- connects to CIN-
1 = Vin- connects to CIN+
CMP2 ~ 0: Comparator Mode Bits.
0 0 0 = Comparator reset (POR default value – low power)
0 0 1 = Comparator with output
0 1 0 = Comparator without output
0 1 1 = Comparator with output and internal reference (Cvref in 99H register)
1 0 0 = Comparator without output and with internal reference (Cvref in 99H register)
1 0 1 = Comparator multiplexed input with internal reference (Cvref in 99H register) and output
1 1 0 = Comparator multiplexed input with internal reference (Cvref in 99H register)
1 1 1 = Comparator off (lowest power)
(19).
(20).
1A ~ 1FH : Unimplemented register.
81H : Option control register.
Bit 7
Bit 6
IES
Bit 5
TCS
Bit 4
TCE
Bit 3
PSC
Bit 2
PS2
Bit 1
PS1
Bit 0
PS0
TMR
/PAPH
Bit
Symbol
Function
Prescaler Value
TMR0 rate
1 : 2
WDT rate
1 : 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 : 4
1 : 2
1 : 8
1 : 4
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 8
2—0
PS2—0
1 : 16
1 : 32
1 : 64
1 : 128
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw P.8 2008/4 Ver. 1.0
MDTIC [ Micon Design Technology Corporation ]
