MDT10F630
WREN : EEPROM Write Enable Bit.
0 = Inhibits write to the data EEPROM
1 = Allows write cycles
WR : Write Control Bit.
0 = Write cycle to the data EEPROM is complete
1 = Initiates a write cycle. (The bit is cleared by hardware once write is complete.
The WR bit can only be set (not clear) in software.)
RD : Read Control Bit.
0 = Does not initiate an EEPROM read.
1 = Initiates an EEPROM read (read takes once cycle. RD is cleared in hardwave.
The RD bit can only be set (not clear) in software.)
(38).
9DH : EEPROM control register 2.
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
EECON2
Write only ; Read as “0”
When write data to the EEPROM must write 55/H to EECON2, and writ AA/H to EECON2 then set WR bit;
the EEPROM can write data inside for write each byte.
Example : Data EEPROM Write
BSR
BCR
BSR
STATUS, PAGE
INTS, GIS
EECON1, WREN
55H
; Select page 1
; Disable interrupt
; Enable write
LDWI
STWR EECON2
LDWI 0AAH
STWR EECON2
BSR EECON1,WR
; Write 55/H
; Write AA/H
; Begin write
(39).
9E ~ 9FH : Unimplemented register.
9. Reset Condition for all Registers
Power-On Reset,
Register
Address
Power range detector
Reset
/MCLR or WDT Reset
Wake-up from SLEEP
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--xx xxxx
0000 0000
uuuu uuuu
0000 0000
000# #uuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
0000 0100
000# #uuu
uuuu uuuu
--uu uuuu
IAR
RTCC
PCL
00h(80h)
01h
02h(82h)
03h(83h)
04h(84h)
05h
STATUS
MSR
PORT A
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw P.12 2008/4 Ver. 1.0
MDTIC [ Micon Design Technology Corporation ]
