MDT10F630
(8). 07H : Port C data output register
Bit 7
-
Bit 6
-
Bit 5
PC5
Bit 4
PC4
Bit 3
PC3
Bit 2
PC2
Bit 1
PC1
Bit 0
PC0
Port C
(9). 08 ~ 09H : Unimplemented Register.
(10).
0AH or 8AH : Program counter high byte.
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCHLAT
PCH4
PCH3
PCH2
PCH1
PCH0
(11).
0BH or 8BH : Interrupt control register.
Bit 7
GIS
Bit 6
PEIE
Bit 5
TIS
Bit 4
INTS
Bit 3
PAIE
Bit 2
TIF
Bit 1
INTF
Bit 0
PAIF
INTS
GIS : Global Interrupt Enable Bit.
0 = Disable all interrupts
1 = Enable all un-masked interrupts
PEIE : Peripheral Interrupt Enable Bit.
0 = Disable all peripheral interrupts
1 = Enable all peripheral interrupts
TIS : TMR0 Overflow Interrupt Enable Bit.
0 = Disable the Timer0 interrupt
1 = Enable the Timer0 interrupt
INTS : PA2/INT Interrupt Enable Bit.
0 = Disable the PA2/INT interrupt
1 = Enable the PA2/INT interrupt
PAIE : PA Port Change Interrupt Enable Bit.
0 = Disable the PA port change interrupt
1 = Enable the PA port change interrupt
TIF : TMR0 Overflow Interrupt Flag Bit.
0 = Timer0 did not overflowed
1 = Timer0 has overflowed (must be cleared in software)
INTF : PA2/INT Interrupt Flag Bit.
0 = The PA2/INT interrupt did not occur
1 = The PA2/INT interrupt occurred
PAIF : PA Port Change Interrupt Flag Bit.
0 = None of the PA5~0 pins have changed state
1 = When at least one of the PA5~0 pins changed state (must be cleared in software)
(12).
0CH : Peripheral interrupt register.
Bit 7
EEIF
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
Bit 2
-
Bit 1
-
Bit 0
PIFB1
CMIF
TMR1IF
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw P.6 2008/4 Ver. 1.0
MDTIC [ Micon Design Technology Corporation ]
