MX25L3205A
Figure 32. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Parallel)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
SCLK
t
Command
3 Dummy Bytes
RES2
SI
23 22 21
3
2
1
0
AB
Electronic Signature Out
High-Z
X
PO7~0
Byte Output
Deep Power-down Mode
Stand-by Mode
NOTES:
1. Under parallel mode, the fastest access clock freg. will be changed to 1.2MHz(SCLK pin clock freg.)
Toreleasefromdeeppower-downmodeandreadID inparallelmode,whichrequiresaparallelmodecommand(55H)
before the read status register command.
Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off.
2.InREADmode,RESmodeandREMSmode,MXICICwillenableoutputanentirecycleinadvancecomparewithother
compatible vendor's spec.
P/N:PM1243
REV. 1.2, NOV. 06, 2006
36
Macronix [ MACRONIX INTERNATIONAL ]
