MX25L3205A
Figure 31. Read Identification (RDID) Sequence (Parallel)
CS#
0
1
2
3
4
5
6
7
8
9 10
SCLK
SI
Command
9F
Manufacturer Identification
High-Z
High-Z
PO7~0
X
Byte output
Device Identification
NOTES:
1. Under parallel mode, the fastest access clock freg. will be changed to 1.2MHz(SCLK pin clock freg.)
To read identification in parallel mode, which requires a parallel mode command (55H) before the read identification
command.
Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off.
2. Only 1~3 bytes would be output for manufacturer and Device ID. It's same for serial RDID mode.
3. In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will
enable output half a cycle in advance compare with other compatible vendor's spec.
P/N:PM1243
REV. 1.2, NOV. 06, 2006
35
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