MX25L3205A
Figure 27. Enter 4Kbit Mode (EN4K) Sequence (Command A5)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
A5
SI
High-Z
SO
Figure 28. Exit 4Kbit Mode (EX4K) Sequence (Command B5)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
B5
SI
High-Z
SO
Note:
Enter and Exit 4kbit mode (EN4K & EX4K)
EN4K and EX4K will not be executed when the chip is in busy state. Enter 4kbit mode then the read and write command
will be executed on this 4kbit. All read and write command sequence is the same as the normal array. The address of
this 4k bits is: A21~A9=0 and A8~A0 customer defined.
Note 1: Chip erase and WRSR will not be executed in 4kbit mode
Note 2: Chip erase can't erase this 4kbit
About the fail status:
Bit6 of the status register is used to state fail status, bit6=1 means program or erase have been failed. Any new write
command will clear this bit.
P/N:PM1243
REV. 1.2, NOV. 06, 2006
32
Macronix [ MACRONIX INTERNATIONAL ]
