MX25L3205A
Figure 30. AUTO PAGE PROGRAM TIMING SEQUENCE (Parallel)
CS#
SCLK
SI
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit7
Bit6 Bit5
Bit4
Hi-Z
1st byte (02h)
PO7,PO6,
…PO0
2nd byte (AD1)
CS#
SCLK
SI
Bit1
Bit0
PO7,PO6,
…PO0
………….
Byte 1Byte
2
4th byte (BA)
CS#
SCLK
SI
Hi-Z
PO7,PO6,
…PO0
………….
Byte N
NOTES:
1. 1st Byte='02h'
2. 2nd Byte=Address 1(AD1), AD23=BIT7, AD22=BIT6, AD21=BIT5, AD20=BIT4,....AD16=BIT0.
3. 3rd Byte=Address 2(AD2), AD15=BIT7, AD14=BIT6, AD13=BIT5, AD12=BIT4,....AD8=BIT0.
4. 4th Byte=Address 3(AD3), AD7=BIT7, AD6=BIT6, ....AD0=BIT0.
5. 5th byte: 1st write data byte.
6. Under parallel mode, the fastest access clock freq. will be changed to 1.2MHz(SCLK pin clock freq.).
7. To program in parallel mode requires a parallel mode command (55H) before the program command.
Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off.
P/N:PM1243
REV. 1.2, NOV. 06, 2006
34
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