MX25L3205A
Figure 29. READ ARRAY SEQUENCE (Parallel)
CS#
SCLK
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4
SI
Hi-Z
PO7,PO6,
…PO0
1st byte (03h)
2nd byte (AD1)
CS#
SCLK
SI
Bit1 Bit0
………….
X
PO7,PO6,
…PO0
Byte 2
Byte 1
4th byte (AD3)
CS#
SCLK
SI
Hi-Z
………….
Byte N
PO7,PO6,
…PO0
NOTES:
1. 1st Byte='03h'
2. 2nd Byte=Address 1(AD1), AD23=BIT7, AD22=BIT6, AD21=BIT5, AD20=BIT4,....AD16=BIT0.
3. 3rd Byte=Address 2(AD2), AD15=BIT7, AD14=BIT6, AD13=BIT5, AD12=BIT4,....AD8=BIT0.
4. 4th Byte=Address 3(AD3), AD7=BIT7, AD6=BIT6, ....AD0=BIT0.
5. From Byte 5, SO Would Output Array Data.
6. Under parallel mode, the fastest access clock freq. will be changed to 1.2MHz(SCLK pin clock freq.).
7. To read array in parallel mode requires a parallel mode command (55H) before the read command.
Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off.
8.InREADmode,RESmodeandREMSmode,MXICICwillenableoutputanentirecycleinadvancecomparewithother
compatible vendor's spec.
P/N:PM1243
REV. 1.2, NOV. 06, 2006
33
Macronix [ MACRONIX INTERNATIONAL ]
