MX25L12835F
9-21. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
32K-byte block erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE32K). Any address of the block (see "Table 4. Memory Organization") is a
valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least
significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte address
on SI→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while during the Block Erase cycle is in progress. The WIP sets during the
tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If
the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Pro-
tect Mode), the Block Erase (BE32K) instruction will not be executed on the block.
Figure 46. Block Erase 32KB (BE32K) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
SCLK
Command
52h
24-Bit Address
A23 A22
A2 A1 A0
SI
MSB
Figure 47. Block Erase 32KB (BE32K) Sequence (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCLK
24-Bit Address
Command
SIO[3:0]
52h A5 A4 A3 A2 A1 A0
MSB
P/N: PM1795
REV. 1.0, OCT. 23, 2012
54
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