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MAX9311EHJ 参数 Datasheet PDF下载

MAX9311EHJ图片预览
型号: MAX9311EHJ
PDF下载: 下载PDF文件 查看货源
内容描述: 1:10差分LVPECL / LVECL / HSTL时钟和数据驱动器 [1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers]
分类和应用: 驱动器逻辑集成电路时钟
文件页数/大小: 12 页 / 370 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
MAX9311/MAX9313
AC ELECTRICAL CHARACTERISTICS
(V
CC
- V
EE
= 2.25V to 3.8V, outputs loaded with 50Ω ±1% to V
CC
- 2V, input frequency = 1.5GHz, input transition time = 125ps
(20% to 80%), CLKSEL = high or low, V
IHD
= V
EE
+ 1.2V to V
CC
, V
ILD
= V
EE
to V
CC
- 0.15V, V
IHD
- V
ILD
= 0.15V to the smaller of 3V or
V
CC
- V
EE
, unless otherwise noted. Typical values are at V
CC
- V
EE
= 3.3V, V
IHD
= V
CC
-1V, V
ILD
= V
CC
-1.5V.) (Note 7)
PARAMETER
Differential
Input-to-
Output Delay
Output-to-
Output Skew
(Note 8)
Part-to-Part
Skew (Note 9)
Added
Random Jitter
(Note 10)
Added
Deterministic
Jitter (Note 10)
SYMBOL CONDITIONS
t
PLHD
,
t
PHLD
-40°C
MIN
220
TYP
321
MAX
380
MIN
220
+25°C
TYP
312
MA
410
MIN
260
+85°C
TYP
322
MAX
400
UNITS
Figure 2
ps
t
SKOO
12
46
12
46
10
35
ps
t
SKPP
f
IN
= 1.5GHz,
Clock pattern
t
RJ
f
IN
= 3.0GHz,
Clock pattern
3Gbps,
2
23
-1 PRBS
pattern
V
OH
- V
OL
350mV, Clock
pattern,
Figure 2
f
MAX
V
OH
- V
OL
500mV, Clock
pattern,
Figure 2
30
1.2
1.2
160
2.5
2.6
30
1.2
1.2
190
2.5
2.6
30
1.2
1.2
140
2.5
ps
ps
(RMS)
2.6
ps
(p-p)
t
DJ
80
95
80
95
80
95
2.0
2.0
3.0
2.0
GHz
Switching
Frequency
1.5
1.5
1.5
Output
Rise/Fall Time
(20% to 80%)
t
R
, t
F
Figure 2
100
112
140
100
116
140
100
121
140
ps
Note 1:
Measurements are made with the device in thermal equilibrium.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:
Single-ended input operation using V
BB
is limited to V
CC
- V
EE
= 3.0V to 3.8V for the MAX9311 and V
CC
- V
EE
= 2.7V to 3.8V
for the MAX9313.
Note 4:
DC parameters production tested at T
A
= +25°C. Guaranteed by design and characterization over the full operating temper-
ature range.
Note 5:
Use V
BB
only for inputs that are on the same device as the V
BB
reference.
Note 6:
All pins open except V
CC
and V
EE
.
Note 7:
Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 8:
Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 9:
Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge
transition.
Note 10:Device
jitter added to the input signal.
4
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