+5V, Serial-Input, Voltage-Output, 14-Bit DACs
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V ± 5%, V
= +ꢂ.5V, AGID = DGID = ±, T = T
A
to T
, unless otherwise noted.)
MAX
DD
REF
MꢁI
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE—REFERENCE SECTION
Reference -3dS Sandwidth
Reference Feedthrough
Lignal-to-Ioise Ratio
SW
Code = FFFC hex
1
1
MHz
mVp-p
dS
Code = ±±±± hex, V
= 1Vp-p at 1±±kHz
REF
LIR
83
75
1ꢂ±
Code = ±±±± hex
Code = FFFC hex
Reference ꢁnput Capacitance
C
ꢁI
pF
STATIC PERFORMANCE—DIGITAL INPUTS
ꢁnput High Voltage
ꢁnput ꢀow Voltage
ꢁnput Current
V
ꢂ.4
V
V
ꢁH
V
±.8
±1
1±
ꢁꢀ
ꢁ
ꢁI
V
= ±
µA
pF
V
ꢁI
ꢁnput Capacitance
Hysteresis Voltage
POWER SUPPLY
Positive Lupply Range
Positive Lupply Current
Power Dissipation
C
(Iote 6)
ꢁI
V
±.4±
H
V
DD
4.75
5.ꢂ5
1.1
V
ꢁ
±.3
1.5
mA
mW
DD
PD
TIMING CHARACTERISTICS
(V
= +5V ± 5%, V
= +ꢂ.5V, AGID = DGID = ±, CMOL inputs, T = T
to T
, unless otherwise noted.)
MAX
DD
REF
A
MꢁI
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
LCꢀK Frequency
f
1±
LCꢀK
LCꢀK Pulse Width High
LCꢀK Pulse Width ꢀow
CS ꢀow to LCꢀK High Letup
CS High to LCꢀK High Letup
LCꢀK High to CS ꢀow Hold
LCꢀK High to CS High Hold
DꢁI to LCꢀK High Letup
DꢁI to LCꢀK High Hold
LDAC Pulse Width
t
45
45
45
45
3±
45
4±
±
CH
t
Cꢀ
ns
t
t
t
ns
CLL±
CLL1
ns
(Iote 6)
MAX545
ns
CLH±
CLH1
t
ns
t
ns
DL
t
ns
DH
t
5±
5±
ns
LDAC
t
MAX545 (Iote 6)
ns
CS High to LDAC ꢀow Letup
ꢀDACL
V
High to CS ꢀow
DD
ꢂ±
µs
(power-up delay)
Note 1: Gain Error tested at V
= ꢂ.±V, ꢂ.5V, and 3.±V.
REF
Note 2: R
tolerance is typically ±ꢂ±%.
OUT
Note 3: Min/max range guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.
Note 4: Reference input resistance is code dependent, minimum at 8554 hex.
Note 5: Llew-rate value is measured from ±% to 63%.
Note 6: Guaranteed by design. Iot production tested.
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3
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
