S P I/Mic ro w ire -Co m p a t ib le
UART in QS OP -1 6
9
Pt
Pt
TX-BUFFER REGISTER
9
MAX310
TX-SHIFT REGISTER
D0t–D7t
TX
SHDN
DIN
X1
B0
B1
B2
B3
CS
XTAL
SPI
BAUD-RATE
GENERATOR
INTERFACE
SCLK
DOUT
RA
FE
ACTIVITY
DETECT
X2
START/STOP-
BIT DETECT
RX-SHIFT REGISTER
D0r–D7r
Pr
RX
9
(SOURCES)
T
R
Pr RA/FE
Pr
Pr
RX-BUFFER REGISTER
RX-BUFFER REGISTER
CTS
RTS
(MASKS)
I / O
TRANSMIT-DONE (TM)
DATA-RECEIVED (RM)
PARITY (PM)
INTERRUPT
LOGIC
9
IRQ
FRAMING ERROR (RAM)/
RECEIVE ACTIVITY
Figure 2. Functional Diagram
6
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