S P I/Mic ro w ire -Co m p a t ib le
UART in QS OP -1 6
Table 5. Bit Descriptions (continued)
BIT
NAME
READ/
WRITE
POR
STATE
DESCRIPTION
Receiver-Activity/Framing-Error Bit. In shutdown mode, this is the RA bit. In normal operation,
this is the FE bit. In shutdown mode, a transition on RX sets RA = 1. In normal mode, a fram-
ing error sets FE = 1. A framing error occurs if a zero is received when the first stop bit is
expected. FE is set when a framing error occurs, and cleared upon receipt of the next proper-
ly framed character independent of the FIFO being enabled. When the device wakes up, it is
likely that a framing error will occur. This error can be cleared with a write configuration. The
FE bit is not cleared on a Read Data operation. When an FE is encountered, the UART resets
itself to the state where it is looking for a start bit.
RA/FE
r
0
MAX310
Software-Shutdown Bit. Enter software shutdown with a write configuration where SHDNi = 1.
Software shutdown takes effect after CS goes high, and causes the oscillator to stop as soon
as the transmitter becomes idle. Software shutdown also clears R, T, RA/FE, D0r–D7r,
D0t–D7t, Pr, Pt, and all data in the receive FIFO. RTS and CTS can be read and updated
while in shutdown. Exit software shutdown with a write configuration where SHDNi = 0. The
oscillator restarts typically within 50ms of CS going high. RTS and CTS are unaffected. Refer
to the Pin Description for hardware shutdown (SHDN input).
Shutdown Read-Back Bit. The read-configuration register outputs SHDNo = 1 when the UART
is in shutdown. Note that this bit is not sent until the current byte in the transmitter is sent (T =
1). This tells the processor when it may shut down the RS-232 driver. This bit is also set imme-
diately when the device is shut down through the SHDN pin.
SHDNi
SHDNo
w
r
0
0
Transmit-Stop Bit. One stop bit will be transmitted when ST = 0. Two stop bits will be transmit-
ted when ST = 1. The receiver only requires one stop bit.
ST
ST
T
w
r
0
0
1
Reads the value of the ST bit.
Transmit-Buffer-Empty Flag. T = 1 means that the transmit buffer is empty and ready to
accept another data word.
r
Transmit-Enable Bit. If TE = 1, then only the RTS pin will be updated on CS’s rising edge. The
contents of RTS, Pt, and D0t–D7t transmit on CS’s rising edge when TE = 0.
w
0
TE
w
r
0
0
TM
TM
Mask for T bit. IRQ is asserted if TM = 1 and T = 1 (Table 6).
Reads the value of the TM bit (Table 6).
PE = 0, L = 0
START D0
D1
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
STOP STOP IDLE
IDLE
IDLE
IDLE
PE = 0, L = 1
START D0
START D0
D1
STOP STOP IDLE
PE = 1, L = 0
D1
D7
Pt
STOP STOP IDLE
PE = 1, L = 1
START D0
D1
Pt
STOP STOP IDLE
IDLE
TIME
SECOND STOP BIT IS OMITTED IF ST = 0.
Figure 5. Parity and Word-Length Control
10 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
