S P I/Mic ro w ire -Co m p a t ib le
UART in QS OP -1 6
MAX310
Table 5. Bit Descriptions
BIT
NAME
READ/
WRITE
POR
STATE
DESCRIPTION
B0–B3
B0–B3
w
r
0000
0000
Baud-Rate Divisor Select Bits. Sets the baud clock’s value (Table 6).
Baud-Rate Divisor Select Bits. Reads the 4-bit baud clock value assigned to these registers.
No
change
Clear-to-Send-Input. Records the state of the CTS pin (CTS bit = 0 implies CTS pin = logic
high).
CTS
r
w
r
Transmit-Buffer Register. Eight data bits written into the transmit-buffer register. D7t is ignored
when L = 1.
D0t–D7t
D0r–D7r
X
Eight data bits read from the receive FIFO or the receive register. These will be all 0s when
the receive FIFO or the receive registers are empty. When L = 1, D7r is always 0.
00000000
w
r
0
0
0
0
FEN
FEN
IR
FIFO Enable. Enables the receive FIFO when FEN = 0. When FEN = 1, FIFO is disabled.
FIFO-Enable Readback. FEN’s state is read.
w
r
Enables the IrDA timing mode when IR = 1.
IR
Reads the value of the IR bit.
Bit for setting the word length of the transmitted or received data. L = 0 results in 8-bit words
(9-bit words if PE = 1), see Figure 5. L = 1 results in 7-bit words (8-bit words if PE = 1).
L
L
w
r
0
0
Reads the value of the L bit.
Transmit-Parity Bit. This bit is treated as an extra bit that will be transmitted if PE = 1. To be
useful in 9-bit networks, the MAX3100 does not calculate parity. If PE = 0, then this bit (Pt) is
ignored in transmit mode (see the Nine-Bit Networks section).
Pt
Pr
w
r
X
X
Receive-Parity Bit. This bit is the extra bit received if PE = 1. Therefore, PE = 1 results in 9-bit
transmissions (L = 0). If PE = 0, then Pr is set to 0. Pr is stored in the FIFO with the receive
data (see the Nine-Bit Networks section).
Parity-Enable Bit. Appends the Pt bit to the transmitted data when PE = 1, and sends the Pt
bit as written. No parity bit is transmitted when PE = 0. With PE = 1, an extra bit is expected to
be received. This data is put into the Pr register. Pr = 0 when PE = 0. The MAX3100 does not
calculate parity.
PE
w
0
PE
PM
PM
r
w
r
0
0
0
Reads the value of the Parity-Enable bit.
Mask for Pr bit. IRQ is asserted if PM = 1 and Pr = 1 (Table 6).
Reads the value of the PM bit (Table 6).
Receive Bit or FIFO Not Empty Flag. R = 1 means new data is available to be read from the
receive register or FIFO.
R
r
0
w
r
0
0
0
0
RM
RM
Mask for R bit. IRQ is asserted if RM = 1 and R = 1 (Table 6).
Reads the value of the RM bit (Table 6).
w
r
RAM
RAM
Mask for RA/FE bit. IRQ is asserted if RAM = 1 and RA/FE = 1 (Table 6).
Reads the value of the RAM bit (Table 6).
Request-to-Send Bit. Controls the state of the RTS output. This bit is reset on power-up (RTS
bit = 0 sets the RTS pin = logic high).
RTS
w
0
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9
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
