欢迎访问ic37.com |
会员登录 免费注册
发布采购

MAX3100CEE 参数 Datasheet PDF下载

MAX3100CEE图片预览
型号: MAX3100CEE
PDF下载: 下载PDF文件 查看货源
内容描述: 在QSOP - 16 SPI / MICROWIRE兼容的UART [SPI/Microwire-Compatible UART in QSOP-16]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路光电二极管数据传输PC时钟
文件页数/大小: 24 页 / 264 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
 浏览型号MAX3100CEE的Datasheet PDF文件第1页浏览型号MAX3100CEE的Datasheet PDF文件第2页浏览型号MAX3100CEE的Datasheet PDF文件第4页浏览型号MAX3100CEE的Datasheet PDF文件第5页浏览型号MAX3100CEE的Datasheet PDF文件第6页浏览型号MAX3100CEE的Datasheet PDF文件第7页浏览型号MAX3100CEE的Datasheet PDF文件第8页浏览型号MAX3100CEE的Datasheet PDF文件第9页  
S P I/Mic ro w ire -Co m p a t ib le  
UART in QS OP -1 6  
MAX310  
ELECTRICAL CHARACTERISTICS (continued)  
(V = +2.7V to +5.5V, T = T  
to T , unless otherwise noted. Typical values are at T = +25°C.)  
MAX A  
A
MIN  
CC  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
AC TIMING (Figure 1)  
CS Low to DOUT Valid  
t
C
= 100pF  
LOAD  
100  
100  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DV  
CLOAD = 100pF, R  
= 10k  
t
CS High to DOUT Tri-State  
CS to SCLK Setup Time  
CS to SCLK Hold Time  
SCLK Fall to DOUT Valid  
DIN to SCLK Setup Time  
DIN to SCLK Hold Time  
SCLK Period  
CS  
TR  
t
100  
0
CSS  
t
CSH  
t
C
= 100pF  
LOAD  
100  
DO  
t
DS  
100  
0
t
DH  
t
CP  
238  
100  
100  
SCLK High Time  
t
CH  
SCLK Low Time  
t
CL  
SCLK Rising Edge  
to CS Falling  
t
t
(Note 1)  
(Note 1)  
100  
ns  
ns  
CS0  
CS1  
CS Rising Edge  
to SCLK Rising  
200  
200  
t
ns  
ns  
ns  
CS High Pulse Width  
Output Rise Time  
Output Fall Time  
CSW  
t
r
10  
10  
TX, RTS, DOUT: C  
= 100pF  
LOAD  
t
f
TX, RTS, DOUT, IRQ: C  
= 100pF  
LOAD  
Note 1: t  
and t  
specify the minimum separation between SCLK rising edges used to write to other devices on the SPI bus  
CS0  
CS1  
and the CS used to select the MAX3100. A separation greater than t  
and t  
ensures that the SCLK edge is ignored.  
CS0  
CS1  
• • •  
CS  
t
t
CH  
t
CSH  
CSS  
t
t
CL  
CSH  
SCLK  
• • •  
t
DS  
t
DH  
DIN  
• • •  
t
DV  
t
DO  
t
TR  
DOUT  
• • •  
Figure 1. Detailed Serial-Interface Timing  
_______________________________________________________________________________________  
3
 复制成功!