S P I/Mic ro w ire -Co m p a t ib le
UART in QS OP -1 6
MAX310
ONE BAUD PERIOD
RX
A
BAUD
BLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MAJORITY
CENTER
SAMPLER
Figure 3. Start-Bit Timing
DATA
UPDATED
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
1
FEN SHDN TM
RM
PM
RAM
0
IR
0
ST
PE
0
L
B3
B2
B1
B0
DIN
DOUT
R
T
0
0
0
0
0
0
0
0
0
0
0
Figure 4. SPI Interface (Write Configuration)
The receiver section receives data in serial form. The
MAX3100 detects a start bit on a high-to-low RX transi-
tion (Figure 3). An internal clock samples data at 16
times the data rate. The start bit can occur as much as
one clock cycle before it is detected, as indicated by
the shaded portion. The state of the start bit is defined
as the majority of the 7th, 8th, and 9th sample of the
inte rna l 16x b a ud c loc k. Sub s e q ue nt b its a re a ls o
majority sampled. Receive data is stored in an 8-word
FIFO. The FIFO is cleared if it overflows.
S P I In t e rfa c e
The bit streams for DIN and DOUT consist of 16 bits,
with b its a s s ig ne d a s s hown in the MAX3100
Operations section. DOUT transitions on SCLK’s falling
edge, and DIN is latched on SCLK’s rising edge (Figure
4). Most operations, such as the clearing of internal
registers, are executed only on CS’s rising edge. The
DIN stream is monitored for its first two bits to tell the
UART the type of data transfer being executed (Write
Config, Read Config, Write Data, Read Data).
The on-b oa rd os c illa tor c a n us e a 1.8432MHz or
3.6864MHz crystal, or it can be driven at X1 with a 45%
to 55% duty-cycle square wave.
Only 16-bit words are expected. If CS goes high in the
middle of a transmission (any time before the 16th bit),
the sequence is aborted (i.e., data does not get written
to individual registers). Every time CS goes low, a new
16-bit stream is expected. An example of a write con-
figuration is shown in Figure 4.
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7
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
