Hig h -S p e e d , Dig it a lly Ad ju s t e d
S t e p -Do w n Co n t ro lle rs fo r No t e b o o k CP Us
0/MAX71
V
BATT
2V TO 28V
R
LIM
V+
I
LIM
TOFF
V
CC
+5V
MAX1710
1-SHOT
TON
5µA
FROM
D/A
ON-TIME
COMPUTE
TRIG
Q
BST
TON
S
Q
Q
TRIG
DH
LX
R
CURRENT
LIMIT
1-SHOT
Σ
OVP
ERROR
AMP
OUTPUT
SKIP
ZERO CROSSING
REF
10k
V
+5V
DD
SHDN
CC
70k
DL
REF
S
Q
PGND
R
g
m
g
m
g
m
FB
GNDS
FBS
FB
REF
+12%
REF
-30%
REF
-5%
CHIP SUPPLY
V
CC
+5V
PGOOD
R-2R
2V
REF
REF
D/A CONVERTER
S1
S2
TIMER
Q
GND
OVP/UVLO
LATCH
D0 D1 D2 D3
Figure 2. MAX1710 Functional Diagram
where I
is 600µA typical, f is the switching frequency,
the filter capacitor’s ESR to act as the current-sense
resistor, so the output ripple voltage provides the PWM
ramp signal. The control algorithm is simple: the high-
side switch on-time is determined solely by a one-shot
whose period is inversely proportional to input voltage
and directly proportional to output voltage. Another one-
shot sets a minimum off-time (400ns typical). The on-time
one-shot is triggered if the error comparator is low, the
CC
and Q
and Q
are the MOSFET data sheet total
G1
G2
gate-charge specification limits at V = 5V.
GS
Fre e -Ru n n in g , Co n s t a n t -On -Tim e P WM
Co n t ro lle r w it h In p u t Fe e d -Fo rw a rd
The QUICK-PWM control architecture is an almost fixed-
frequency, constant-on-time current-mode type with volt-
age feed-forward (Figure 2). This architecture relies on
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