Lo w -Vo lt a g e , P re c is io n S t e p -Do w n
Co n t ro lle r fo r P o rt a b le CP U P o w e r
MAX136
determined by the input voltage and load current, with
Designers of RF communicators or other noise-sensi-
tive analog equipment should be conservative and stay
within the guidelines. Designers of notebook computers
and similar commercial-temperature-range digital sys-
the worst case occurring at V = 2 x V
:
IN
OUT
I
= I
×
V
V
− V
/V
IN
(
)
RMS
LOAD
OUT IN
OUT
tems can multiply the R
value by a factor of 1.5
ESR
without hurting stability or transient response.
Therefore, when V is 2 x V
:
IN
OUT
The output voltage ripple, which is usually dominated
by the filter capacitor’s ESR, can be approximated as
I
= I
/ 2
RMS
LOAD
I
x R
. There is also a capacitive term, so the
ESR
RIPPLE
full equation for ripple in continuous-conduction mode
is V = I x [R + 1 / (2 x p x f x
Ou t p u t Filt e r Ca p a c it o r Va lu e
The output filter capacitor values are generally deter-
mined by the ESR and voltage-rating requirements
rather than actual capacitance requirements for loop
stability. In other words, the low-ESR electrolytic capac-
itor that meets the ESR requirement usually has more
output capacitance than is required for AC stability.
Use only specialized low-ESR capacitors intended for
switching-regulator applications, such as AVX TPS,
Sprague 595D, Sanyo OS-CON, or Nichicon PL series.
To ensure stability, the capacitor must meet both mini-
mum capacitance and maximum ESR values as given
in the following equations:
NOISE(p -p )
RIPPLE
ESR
C
)]. In Idle Mode, the inductor current becomes
OUT
discontinuous, with high peaks and widely spaced
pulses, so the noise can actually be higher at light load
(compared to full load). In Idle Mode, calculate the out-
put ripple as follows:
0.02 x R
ESR
V
=
+
NOISE(p−p)
R
SENSE
0.0003 x L x 1/V
+ 1/ V − V
(
)
]
OUT
IN
OUT
[
2
R
x C
F
(
)
SENSE
C
> V (1 + V
/ V
) / V
x R
x f
SENSE
OUT
REF
OUT
IN(MIN)
OUT
S e le c t in g Ot h e r Co m p o n e n t s
R
ESR
< R
x V
/ V
SENSE
OUT REF
MOSFET Switches
The high-current N-channel MOSFETs must be logic-
level types with guaranteed on-resistance specifica-
where R
below.
can be multiplied by 1.5, as discussed
ESR
These equations are worst case, with 45 degrees of
p ha s e ma rg in to e ns ure jitte r-fre e , fixe d -fre q ue nc y
op e ra tion, a nd p rovid e a nic e ly d a mp e d outp ut
response for zero to full-load step changes. Some cost-
conscious designers may wish to bend these rules with
less-expensive capacitors, particularly if the load lacks
large step changes. This practice is tolerable if some
b e nc h te s ting ove r te mp e ra ture is d one to ve rify
acceptable noise and transient response.
tions a t VGS
=
4.5V. Lowe r g a te -thre s hold
specifications are better (i.e., 2V max rather than 3V
max). Drain-source breakdown voltage ratings must at
least equal the maximum input voltage, preferably with
a 20% derating factor. The best MOSFETs have the
lowest on-resistance per nanocoulomb of gate charge.
Multiplying R
by Q provides a good figure of
DS(ON)
g
merit for comparing various MOSFETs. Newer MOSFET
process technologies with dense cell structures gener-
ally perform best. The internal gate drivers tolerate
>100nC total gate charge, but 70nC is a more practical
upper limit to maintain best switching times.
No well-defined boundary exists between stable and
unstable operation. As phase margin is reduced, the
first symptom is timing jitter, which shows up as blurred
edges in the switching waveforms where the scope
does not quite sync up. Technically speaking, this jitter
(usually harmless) is unstable operation, since the duty
factor varies slightly. As capacitors with higher ESRs
are used, the jitter becomes more pronounced, and the
load-transient output voltage waveform starts looking
ragged at the edges. Eventually, the load-transient
waveform has enough ringing on it that the peak noise
levels exceed the allowable output voltage tolerance.
Note that even with zero phase margin and gross insta-
bility, the output voltage noise never gets much worse
In high-current applications, MOSFET package power
dissipation often becomes a dominant design factor.
2
I R power losses are the greatest heat contributor for
2
both high-side and low-side MOSFETs. I R losses are
distributed between Q1 and Q2 according to duty fac-
tor as shown in the equations below. Generally, switch-
ing losses affect only the upper MOSFET, since the
Schottky rectifier usually clamps the switching node
before the synchronous rectifier turns on. Gate-charge
losses are dissipated by the driver and do not heat the
MOSFET. Calculate the temperature rise according to
package thermal-resistance specifications to ensure
than I
x R
(under constant loads).
PEAK
ESR
______________________________________________________________________________________ 19
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
