Lo w -Vo lt a g e , P re c is io n S t e p -Do w n
Co n t ro lle r fo r P o rt a b le CP U P o w e r
Ringing at the high-side MOSFET gate (DH) in discon-
tinuous-conduction mode (light loads) is a natural oper-
ating condition. It is caused by residual energy in the
tank circuit, formed by the inductor and stray capaci-
tance at the switching node, LX. The gate-drive nega-
tive rail is referred to LX, so any ringing there is directly
coupled to the gate-drive output.
PWM comparator, with the gain weighted so that the
integrated signal has only enough gain to correct the
DC inaccuracies. The integrator’s response time is
determined by the time constant set by the capacitor
placed on the CC pin. The time constant should not be
so fast that the integrator responds to the normal V
OUT
ripple or too slow to negate the integrator’s effect. A
470pF to 1500pF CC capacitor is sufficient for 200kHz
to 300kHz frequencies.
Cu rre n t -Lim it in g a n d Cu rre n t -S e n s e In p u t s
(CS H a n d CS L)
MAX136
Figure 5 shows the output voltage response to a 0A to
3A load transient with and without the integrator. With
the integrator, the output voltage returns to within 0.1%
of its no-load value with only a small AC excursion.
Without the inte g ra tor, the typ ic a l loa d -tra ns ie nt
response with the AC and DC output voltage changes.
Asymmetrical clamping at the integrator output pre-
ve nts wors e ning of loa d tra ns ie nts d uring p uls e -
skipping mode.
The current-limit circuit resets the main PWM latch and
turns off the high-side MOSFET switch whenever the
voltage difference between CSH and CSL exceeds
100mV. This limiting is effective for both current flow
directions, putting the threshold limit at ±100mV. The
tolerance on the positive current limit is ±20%, so the
external low-value sense resistor (R1) must be sized for
80mV/I
, where I
is the required peak inductor
PEAK
PEAK
current to support the full load current. Components
mus t b e d e s ig ne d to withs ta nd c ontinuous c urre nt
stresses of 120mV/R1.
In t e rn a l Dig it a l S o ft -S t a rt Circ u it
Soft-start allows a gradual increase of the internal cur-
rent-limit level at start-up to reduce input surge cur-
rents. The SMPS contains an internal digital soft-start
circuit controlled by a counter, a digital-to-analog con-
verter (DAC), and a current-limit comparator. In shut-
down or standby mode, the soft-start counter is reset to
zero. When the SMPS is enabled, its counter starts
counting oscillator pulses, and the DAC begins incre-
menting the comparison voltage applied to the current-
limit comparator. The DAC output increases from 0mV
to 100mV in five equal steps as the count increases to
512 c loc ks . As a re s ult, the ma in outp ut c a p a c itor
charges up relatively slowly. The exact time of the out-
put rise depends on output capacitance and load cur-
rent, but it is typically 1ms with a 300kHz oscillator.
For breadboarding or for very high current applications,
it may be useful to wire the current-sense inputs with a
twis te d p a ir ra the r tha n PC tra c e s (two p ie c e s of
wra p p e d wire twis te d tog e the r a re s uffic ie nt.) This
reduces the noise picked up at CSH and CSL, which
can cause unstable switching and reduced output cur-
rent.
Os c illa t o r Fre q u e n c y a n d S yn c h ro n iza t io n
(S YNC)
The SYNC input controls the oscillator frequency. Low
selects 200kHz; high selects 300kHz. SYNC can also
be used to synchronize with an external 5V CMOS or
TTL clock generator. SYNC has a guaranteed 240kHz
to 340kHz capture range. A high-to-low transition on
SYNC initiates a new cycle.
Ove rlo a d a n d Dro p o u t Op e ra t io n
Drop out (low inp ut-outp ut d iffe re ntia l) op e ra tion is
e nha nc e d b y s tre tc hing the c loc k p uls e wid th to
increase the maximum duty factor. The algorithm fol-
Operation at 300kHz optimizes the application circuit
for component size and cost. Operation at 200kHz pro-
vid e s inc re a s e d e ffic ie nc y, lowe r d rop out, a nd
improved load-transient response at low input-output
voltage differences (see the Low-Voltage Operation
section).
lows: If the output voltage (V ) drops out of regula-
OUT
tion without the current limit having been reached, the
SMPS skips an off-time period (extending the on-time).
At the end of the cycle, if the output is still out of regula-
tion, the SMPS s kip s a nothe r off-time p e riod . This
action can continue until three off-time periods are
skipped, effectively dividing the clock frequency by as
much as four. This behavior also slightly improves load-
transient response. Dividing the clock frequency by
four raises the maximum duty factor to above 98%. The
typical PWM minimum off-time is 300ns, regardless of
the operating frequency.
Ou t p u t Vo lt a g e Ac c u ra c y (GND, CC)
Output voltage error is guaranteed to be within ±1%
over all conditions of line, load, and temperature. The
DC load regulation is typically better than 0.1% due to
the integrator amplifier. Transient response is optimized
by providing a feedback signal that has a direct path
from the output to the main summing PWM comparator.
The integrated feedback signal is also summed into the
16 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
