Lo w -Vo lt a g e , P re c is io n S t e p -Do w n
Co n t ro lle r fo r P o rt a b le CP U P o w e r
Table 4. Powering the MAX1636
V
V+
CONNECTS
TO
VL
CONNECTS
TO
CC
AVAILABLE
POWER SOURCES
CONNECTS
TO
COMMENT
Battery, 3.3V, and 5V
Battery and 5V
Battery and 3.3V
Battery only
3.3V
5V
5V
5V
5V
Most efficient
5V
3.3V
VL
Battery
Battery
Bypass capacitor only
Bypass capacitor only
MAX136
Least efficient
REF a n d VL S u p p lie s a n d V
In p u t
Standby operation is entered when SHDN = low and
OVP = high (Table 5). In standby mode, the VL regula-
tor stays active, and the DL output is forced high to
provide overvoltage protection by clamping the output
to GND. However, DL is not forced high until the output
CC
The 1.1V reference (REF) is accurate to ±1% over tem-
perature, making REF useful as a precision system ref-
e re nc e . Byp a s s REF to GND with a 0.22µF (min)
c a p a c itor. REF c a n supp ly up to 50µA for e xte rna l
loads. Loading REF reduces the main output voltage
slightly because of the reference load-regulation error.
The 5V VL linear-regulator output can be tied to the
system +5V supply in order to obtain gate-drive power
sags below V , so that the output can be held high
REF
by external keep-alive supplies.
RESET P o w e r-Go o d Vo lt a g e Mo n it o r
The power-good monitor generates a system-reset sig-
nal. The RESET output is an open drain that needs to
be pulled up to the appropriate logic supply. At first
power-up, RESET is held low until output is in regula-
tion. At this point, an internal timer begins counting
oscillator pulses, and RESET continues to be held low
until 32,000 cycles have elapsed. After this timeout
period (107ms at 300kHz or 160ms at 200kHz), the
RESET output is released.
from an efficient source. The two supply pins (V and
CC
VL) a re ind e p e nd e nt of e a c h othe r (no p rote c tion
diodes or sequencing requirements), allowing you to
choose the most efficient sources for chip biasing from
among existing system supply voltages without having
to worry a b out s e q ue nc ing or la tc h-up p rob le ms
(Table 4).
The V
inp ut runs the c hip if the V
volta g e is
CC
CC
greater than 3.15V. Otherwise, the chip supply is pow-
ered from VL via the internal V -VL switchover circuit.
If a system supply between 3.3V and 5V is not avail-
CC
Ou t p u t Un d e rvo lt a g e Lo c k o u t
The output undervoltage-lockout circuit is similar to
foldback current limiting but employs a timer rather
than a variable current limit. The SMPS has an under-
voltage-protection circuit that is activated 6144 clock
cycles after the SMPS is enabled. If the SMPS output is
under 70% of the nominal value, output is latched off
and does not restart until SHDN is toggled or until V+
power is cycled below 1V. Note that undervoltage pro-
tection can make prototype troubleshooting difficult,
since only 20ms or 30ms elapse before the SMPS is
latched off.
able, tie V directly to VL.
CC
In shutdown mode, the VL regulator and reference are
completely turned off. In standby mode, the VL regula-
tor and DL stay alive so that the overvoltage-protection
circuit can operate (Table 5).
Important: Ensure that VL and V do not exceed 6V.
CC
Measure VL with the main output fully loaded. If it is
p ump e d a b ove 5.5V, e ithe r e xc e s s ive b oos t-d iod e
capacitance or excessive ripple at V+ is the probable
cause. Use only small-signal diodes for the boost cir-
c uit (10mA to 100mA Sc hottky or 1N4148 a re p re-
ferred) and bypass VL to PGND with a 4.7µF capacitor
directly at the package pins.
The outp ut und e rvolta g e loc kout c irc uit p rote c ts
against heavy overloads and shorts to the main SMPS
output. The circuit trips if the output is less than 70% of
the nominal output value any time after the timeout has
expired upon start-up. When the comparator trips, the
output is turned off (the SMPS stops switching). This
state is similar to thermal shutdown and can be exited
by a power-on reset or by a rising edge on SHDN. The
overvoltage crowbar is disabled in output undervoltage
or thermal shutdown modes.
S h u t d o w n a n d S t a n d b y Mo d e s
Holding SHDN low puts the IC into its 3µA shutdown
mode. SHDN is a logic input with a threshold of about
1V (the VTH of an internal N-channel MOSFET). For
automatic start-up, tie SHDN to V+.
14 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
