MAX11329–MAX11332
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Pin Description (continued)
MAX11329
MAX11331
MAX11330
MAX11332
NAME
FUNCTION
(16 CHANNEL) (8 CHANNEL)
Power-Supply Input. Bypass to GND with a 10FF in parallel with a 0.1FF
capacitors.
20, 21
22
20, 21
22
V
DD
SCLK
Serial Clock Input. Clocks data in and out of the serial interface.
Active-Low Chip Select Input. When CS is low, the serial interface is enabled.
When CS is high, DOUT is high impedance or three-state.
23
23
CS
Serial Data Input. DIN data is latched into the serial interface on the rising edge
of SCLK.
24
25
26
24
25
26
DIN
DGND
OVDD
Digital I/O Ground
Digital Power-Supply Input. Bypass to GND with a 10FF in parallel with a 0.1FF
capacitors.
Serial Data Output. Data is clocked out on the falling edge of SCLK. When CS is
high, DOUT is high impedance or three-state.
27
27
DOUT
End of Conversion Output. Data is valid after EOC is driven low (internal clock mode
only).
28
—
28
—
EOC
EP
Exposed Pad. Connect EP directly to GND plane for guaranteed performance.
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