DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Figure 18-11. Transmit-Side Interleave Bus Operation, Byte Mode
TSYNC
1
FR1 CH32
FR1 CH32
FR0 CH1
FR0 CH1
FR1 CH1
FR1 CH1
FR0 CH2
FR0 CH2
FR1 CH2
FR1 CH2
TSER
1
TSIG
TSER2
TSIG2
FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2
FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2
BIT DETAIL
SYSCLK
3
TSYNC
FRAMER 1, CHANNEL 1
FRAMER 1, CHANNEL 1
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
FRAMER 0, CHANNEL 1
MSB
LSB
LSB
MSB
LSB
TSER
TSIG
FRAMER 3, CHANNEL 32
A
B
C/A D/B
A
B
C/A D/B
A
B
C/A D/B
NOTE 1: 4.096MHz BUS CONFIGURATION.
NOTE 2: 8.192MHz BUS CONFIGURATION.
NOTE 3: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0).
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
