DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Figure 18-12. Transmit-Side Interleave Bus Operation, Frame Mode
TSYNC
1
FR1 CH1-32
FR1 CH1-32
FR0 CH1-32
FR0 CH1-32
FR1 CH1-32
FR1 CH1-32
FR0 CH1-32
FR0 CH1-32
FR1 CH1-32
FR1 CH1-32
TSER
1
TSIG
TSER2
TSIG2
FR0 CH1-32
FR3 CH1-32
FR3 CH1-32
FR3 CH1-32
FR3 CH1-32
FR2 CH1-32
FR2 CH1-32
FR1 CH1-32 FR2 CH1-32
FR1 CH1-32 FR2 CH1-32
FR0 CH1-32 FR1 CH1-32 FR2 CH1-32
FR3 CH1-32
FR0 CH1-32 FR1 CH1-32 FR2 CH1-32
FR0 CH1-32
FR3 CH1-32
BIT DETAIL
SYSCLK
TSYNC3
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
FRAMER 0, CHANNEL 1
FRAMER 0, CHANNEL 2
FRAMER 0, CHANNEL 2
MSB
LSB
LSB
MSB
LSB
TSER
TSIG
FRAMER 3, CHANNEL 32
A
B
C/A D/B
A
B
C/A D/B
A
B
C/A D/B
NOTE 1: 4.096MHz BUS CONFIGURATION.
NOTE 2: 8.192MHz BUS CONFIGURATION.
NOTE 3: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0).
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
