78M6610+LMU Data Sheet
Read Operations
Read operations are initiated in the same way as write operations with the exception that the R/Wbit of
the control byte is set to one. There are two basic types of read operations: current address read and
random read.
Current Address Read: the 78M6610+LMU contains an address counter that maintains the address of the
last register accessed, internally incremented by one when the stop bit is received. Therefore, if the
previous read access was to register address n, the next current address read operation would access
data from address n + 1.
Upon receipt of the control byte with R/Wbit set to one, the 78M6610+LMU issues an acknowledge (A)
and transmits the eight bit data byte. The master will not acknowledge the transfer, but generates a STOP
condition to end the transfer and the 78M6610+LMU will discontinue the transmission.
S
Device Address
1
Data
Data
Data
P
0
1
2
3
4
5 6
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1 2 3 4 5 6 7
0
0
0
A
C
K
S
T
A
R
T
S
T
O
P
A
C
K
A
C
K
N
O
A
C
K
Figure 40. Read Operation
This read operation is not limited to 3 bytes but can be extended until the register address pointer
reaches its maximum value. If the register address pointer has not been set by previous operations, it is
necessary to set it issuing a command as follows:
S
Device Address
0
S
Register Address (n)
P
0
1
2
3
4
5
6
0 1 2 3 4 5 6 7
A
C
K
A
C
K
S
T
A
R
T
S
T
O
P
Figure 41. Setting Read Address
Random Read: random read operations allow the master to access any register in a random manner. To
perform this operation, the register address must be set as part of the write operation. After the address is
sent, the master generates a start condition following the acknowledge response. This sequence
completes the write operation. The master should issue the control byte again this time, with the R/Wbit
set to 1 to indicate a read operation. The 78M6610+LMU will issue the acknowledge response, and
transmit the data. At the end of the transaction the master will not acknowledge the transfer and generate
a STOP condition.
S
R
S
Device Address
0
S
Register Address (n)
Device Address
1
Data
S
Data
Data
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
1 2 3 4 5 6 7
0
S
T
A
R
T
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
N
O
S
T
A
R
T
A
C
K
Figure 42. Reading Multiple Registers
This read operation is not limited to 3 bytes but can be extended until the register address pointer
reaches its maximum value.
61
Rev 0
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