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78M6610LMU 参数 Datasheet PDF下载

78M6610LMU图片预览
型号: 78M6610LMU
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量处理器的负荷监测单位 [Energy Measurement Processor for Load Monitoring Units]
分类和应用: 监控
文件页数/大小: 63 页 / 1710 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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78M6610+LMU Data Sheet  
Write Operations  
Following the START (S) condition from the master, the device address (7-bits) and the R/Wbit (logic low  
for write) are clocked onto the bus by the master. This indicates to the addressed slave receiver that the  
register address will follow after it has generated an acknowledge bit (A) during the ninth clock cycle.  
Therefore, the next byte transmitted by the master is the register address and will be written into the  
address pointer of the 78M6610+LMU. After receiving another acknowledge (A) signal from the  
78M6610+LMU, the master device will transmit the data byte(s) to be written into the addressed memory  
location. The data transfer ends when the master generates a stop (P) condition. This initiates the internal  
write cycle. The example below shows a 3-byte data write (24-bit register write).  
S
Device Address  
0
Register Address  
Data  
Data  
Data  
P
0
1
2
3
4
5
6
0
1 2 3 4 5 6 7  
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1 2 3 4 5 6 7  
0
0
0
A
C
K
A
C
K
S
T
A
R
T
S
T
O
P
A
C
K
A
C
K
A
C
K
Figure 38. Write Operation Single Register  
Upon receiving a STOP (P) condition, the internal register address pointer will be incremented. The write  
access can be extended to multiple sequential registers. The figure below shows a single transaction with  
multiple registers written sequentially.  
REGISTER (n+1)  
REGISTER (n)  
REGISTER (n+2) REGISTER (n+x)  
P
S
Device Address  
0
Data  
Data  
Data  
Register Address (n)  
0
1 2 3 4  
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
4
6 7  
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1
0
2
3
4
5
6
7
6 7  
0
0
A
C
K
A
C
K
S
T
A
R
T
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 39. Write Operation Multiple Registers  
60  
Rev 0