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78M6610LMU 参数 Datasheet PDF下载

78M6610LMU图片预览
型号: 78M6610LMU
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量处理器的负荷监测单位 [Energy Measurement Processor for Load Monitoring Units]
分类和应用: 监控
文件页数/大小: 63 页 / 1710 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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78M6610+LMU Data Sheet  
SPI Interface  
The 78M6610+LMU SPI can be configured as slave only. Once the SPI interface is activated, it utilizes  
the following pins:  
SSB:  
SCK:  
SDO:  
SDI:  
Slave select (SS) is an input and active low signal  
Serial Data Clock (SCK) input  
Master Input/Slave Output (MISO), serial data output  
Master Output/Slave Input (MOSI), serial data input  
Clock Polarity and Phase  
The figure below shows a single-byte transaction on the SPI bus. The data is shifted on the falling edge of  
the serial data clock and latched (captured) on the rising edge.  
SCK  
MSB  
MSB  
6
6
5
5
4
4
3
3
2
2
1
1
LSB  
SDI (Master Output)  
SDO (Master Input)  
SSB (To Slave)  
LSB  
Figure 31. SPI Interface  
SPI Protocol  
The SPI allows access to the 78M6610+LMU registers. The first byte that the master needs to transmit to  
the 78M6610+LMU (slave) is the control byte. The control byte allows setting the number of words to be  
transferred and the most significant bits of the register address:  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1 Bit 0  
NBRACC[3:0]  
ADDR7 ADDR6  
0
1
ADDR7 and ADDR6 bits select bit 7 and 6 of the 8-bit register address to be accessed by the following  
data transactions. The read and write register are contained in a 256 words (24-bit) area of the on-chip  
RAM.  
NBRACC[3:0] represents the number of words (3-bytes) accesses to be performed by subsequent data  
transactions. The actual number of data addresses accessed per data transaction is NBRACC + 1. For  
single address access, the field is set at 0. NBRACC is reset to 0 when the operation (multiple reads or  
writes) is completed. NBRACC must be set to a nonzero value prior to each multiple word transaction.  
55  
Rev 0