78M6610+LMU Data Sheet
I2C Interface
The 78M6610+LMU has an I2C interface available at the SDAI, SDAO, and SCL pins. The interface
supports I2C slave mode with a 7-bit address and operates at a data rate up to 400kHz. The figure below
shows two possible configurations. Configuration A is the standard configuration. The double pin for SDA
also allows for isolated configuration B.
V3P3 or 5VDC
5VD
C
SDAi
V3P3 or 5VDC
SDA
SDA
SDAi
V
3P3 or 5VDC
I2C_GND
SDAo
SDAo
SCK
5VDC
SCK
SCK
SCK
A) STANDARD CONFIGURATION
B) ISOLATED CONFIGURATION
Figure 34. I2C Interface
Device Address Configuration
By default, there are only four possible addresses for the MAX78615+LMU as defined by two external
address pins. To expand the potential address of the device to the entire 7-bit address range for I2C, one
can set I2C address bits 6 through 2 in the DEVADDR register and save them to Flash memory as the
default.
A change in the device address takes effect following a power-on or reset. During the initialization, the
DEVADDR register value is restored from Flash memory and the state of the address pins are acquired.
DEVADDR bits 23 through 5 are not used and have no effect on the device address.
I2C Device Address
6
5
4
3
2
1
0
DEVADDR Register bit 4:0
MP6/ADDR1 Pin
SPCK/ADDR0 Pin
Figure 35. I2C Device Address
58
Rev 0
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
