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78M6610LMU 参数 Datasheet PDF下载

78M6610LMU图片预览
型号: 78M6610LMU
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量处理器的负荷监测单位 [Energy Measurement Processor for Load Monitoring Units]
分类和应用: 监控
文件页数/大小: 63 页 / 1710 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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78M6610+LMU Data Sheet  
Bus Characteristics  
A data transfer may be initiated only when the bus is not busy.  
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in  
the data line while the clock line is HIGH will be interpreted as a START or STOP condition.  
Bus Conditions:  
Bus Not Busy (I): Both data and clock lines are HIGH indicating an Idle Condition.  
Start Data Transfer (S): A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH  
determines a START condition. All commands must be preceded by a START condition.  
Stop Data Transfer (P): A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH  
determines a STOP condition. All operations must be ended with a STOP condition.  
Data Valid: The state of the data line represents valid data when, after a START condition, the data  
line is stable for the duration of the HIGH period of the clock signal. The data on the line must be  
changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each  
data transfer is initiated with a START condition and terminated with a STOP condition.  
Acknowledge (A): Each receiving device, when addressed, is obliged to generate an acknowledge  
after the reception of each byte. The master device must generate an extra clock pulse, which is  
associated with this Acknowledge bit. The device that acknowledges has to pull down the SDA line  
during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH  
period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into  
account. During reads, a master must signal an end of data to the slave by not generating an  
Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave  
(78M6610+LMU) will leave the data line HIGH to enable the master to generate the STOP condition.  
MSB  
SDA  
9
ACK  
9
ACK  
1
7
8
SCL  
2
SCL may be held low by  
slave to service interrupts  
Start Bit  
Start or Stop Bits  
Figure 36. I2C Bus Characteristics  
Device Addressing  
A control byte is the first byte received following the START condition from the master device.  
The control byte consists of a seven bit address and a bit (LSB) indicating the type of access (0 = write; 1  
= read).  
DEVICE ADDRESS  
LSB  
X
MSB  
X
S
X
X
X
X
X
R/W ACK  
READ/WRITE  
ACKNOWLEDGE  
START BIT  
Figure 37. I2C Device Addressing  
59  
Rev 0