78M6610+LMU Data Sheet
Example 3: Noncontiguous Read accesses of address 0x17 and 0x0A.
Byte# Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
NbrAcc[3:0] = 0x00
Addr7 = Addr6 =
0
0
0
2
Addr[5:0] = 0x17
RD =
0
0
3
4
5
6
Data[23:16] @ 0x17
Data[15:8] @ 0x17
Data[7:0] @ 0x17
NbrAcc[3:0] = 0x00
Addr7 = Addr6 =
0
1
0
0
0
7
8
Addr[5:0] = 0x0A
W = 1
Data[23:16] @ 0x0A
Data[15:8] @ 0x0A
Data[7:0] @ 0x0A
9
10
The timing of the transaction can be organized in different ways depending on the host capabilities. The
above transaction can be a succession of bytes as shown in the diagram below. Those bytes are carried
by a continuously active SCK, with eight clock periods per byte.
SDI
SDO
SCK
Byte 1: Control
Byte 2: Addr & Ctrl
Byte 3: Data[23:16]
HiZ
Byte 4: Data[15:8]
Byte 5: Data[7:0]
SCK Active
SSB
Figure 32. SPI Timing Continuous Clock
The host also has the possibility to space out the bytes transmitted. In such a case, SCK is inactive
during the “in-between-bytes” gap, as illustrated below. Note that the figure shows two gaps, one between
the configuration and the data transactions and another between bytes within the data transaction. The
placement of those gaps is strictly for the purpose of illustrating the concept.
SDI
SDO
SCK
SSB
Byte 1: Control
Byte 2: Addr & Ctrl Byte 3: Data[23:16] Byte 4: Data[15:8]
HiZ
Byte 5: Data[7:0]
SCK Active
SCK Active
SCK Active
Figure 33. SPI Timing Gapped Clock
57
Rev 0
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
