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71M6543H 参数 Datasheet PDF下载

71M6543H图片预览
型号: 71M6543H
PDF下载: 下载PDF文件 查看货源
内容描述: 可选增益1或8的一个电流电能表计量芯片的补偿 [Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation]
分类和应用:
文件页数/大小: 157 页 / 2164 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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71M6543F/H and 71M6543G/GH Data Sheet  
Delay compensation and other functions in the CE code require the settings for MUX_DIV[3:0],  
MUXn_SEL[3:0], RMT_E, FIR_LEN[1:0], ADC_DIV and PLL_FAST to be fixed for a given CE code.  
Refer to Table 1 and Table 2 for the settings that are applicable to the 71M6543.  
Table 3 summarizes the I/O RAM registers used for configuring the multiplexer, signals pins, and ADC. All  
listed registers are 0 after reset and wake from battery modes, and are readable and writable.  
Table 3: Multiplexer and ADC Configuration Bits  
Name  
Location Description  
MUX0_SEL[3:0]  
MUX1_SEL[3:0]  
MUX2_SEL[3:0]  
MUX3_SEL[3:0]  
MUX4_SEL[3:0]  
MUX5_SEL[3:0]  
MUX6_SEL[3:0]  
MUX7_SEL[3:0]  
MUX8_SEL[3:0]  
MUX9_SEL[3:0]  
2105[3:0] Selects the ADC input converted during time slot 0.  
2105[7:4] Selects the ADC input converted during time slot 1.  
2104[3:0] Selects the ADC input converted during time slot 2.  
2104[7:4] Selects the ADC input converted during time slot 3.  
2103[3:0] Selects the ADC input converted during time slot 4.  
2103[7:4] Selects the ADC input converted during time slot 5.  
2102[3:0] Selects the ADC input converted during time slot 6.  
2102[7:0] Selects the ADC input converted during time slot 7.  
2101[3:0] Selects the ADC input converted during time slot 8.  
2101[7:0] Selects the ADC input converted during time slot 9.  
MUX10_SEL[3:0] 2100[3:0] Selects the ADC input converted during time slot 10.  
Controls the rate of the ADC and FIR clocks.  
ADC_DIV  
MUX_DIV[3:0]  
PLL_FAST  
FIR_LEN[1:0]  
DIFF0_E  
2200[5]  
2100[7:4] The number of ADC time slots in each multiplexer frame (maximum = 11).  
Controls the speed of the PLL and MCK.  
Determines the number of ADC cycles in the ADC decimation FIR filter.  
2200[4]  
210C[2:1]  
210C[4]  
210C[5]  
210C[6]  
210C[7]  
Enables the differential configuration for analog input pins IADC0-IADC1 .  
Enables the differential configuration for analog input pins IADC2-IADC3 .  
Enables the differential configuration for analog input pins IADC4-IADC5 .  
Enables the differential configuration for analog input pins IADC6-IADC7 .  
DIFF2_E  
DIFF4_E  
DIFF6_E  
Enables the remote sensor interface transforming pins IADC2-IADC3 into a digital  
interface for communications with a 71M6xx3 sensor.  
RMT2_E  
RMT4_E  
2709[3]  
2709[4]  
Enables the remote sensor interface transforming pins IADC4-IADC5 into a digital  
interface for communications with a 71M6xx3 sensor.  
Enables the remote sensor interface transforming pins IADC6-IADC7 into a digital  
interface for communications with a 71M6xx3 sensor.  
RMT6_E  
PRE_E  
2709[5]  
2704[5]  
Enables the 8x pre-amplifier.  
Refer to Table 71 starting on page 104 for more complete details about these I/O RAM locations.  
2.2.3 Delay Compensation  
When measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that  
phase must be sampled at the same instant. Otherwise, the phase difference, Ф, introduces errors.  
tdelay  
φ =  
360o = tdelay f 360o  
T
Where f is the frequency of the input signal, T = 1/f and tdelay is the sampling delay between current and  
voltage.  
Traditionally, sampling is accomplished by using two A/D converters per phase (one for voltage and the  
other one for current) controlled to sample simultaneously. Teridian’s Single-Converter Technology®,  
however, exploits the 32-bit signal processing capability of its CE to implement “constant delay” all-pass  
filters. The all-pass filter corrects for the conversion time difference between the voltage and the  
corresponding current samples that are obtained with a single multiplexed A/D converter.  
The “constant delay” all-pass filter provides a broad-band delay 360o - θ, which is precisely matched to  
the difference in sample time between the voltage and the current of a given phase. This digital filter does  
not affect the amplitude of the signal, but provides a precisely controlled phase response.  
v1.2  
© 2008–2011 Teridian Semiconductor Corporation  
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