71M6543F/H and 71M6543G/GH Data Sheet
Multiplexer advance, FIR initiation and chopping of the ADC reference voltage (using the internal CROSS
signal, see 2.2.7 Voltage References) are controlled by the internal MUX_CTRL circuit. Additionally,
MUX_CTRL launches each pass of the CE through its code. MUX_CTRL is clocked by CK32, the 32768 Hz
clock from the PLL block. The behavior of the MUX_CTRL circuit is governed by:
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CHOP_E[1:0] (I/O RAM 0x2106[3:2])
MUX_DIV[3:0] (I/O RAM 0x2100[7:4])
FIR_LEN[1:0] (I/O RAM 0x210C[2:1])
ADC_DIV (I/O RAM 0x2200[5])
The duration of each multiplexer state depends on the number of ADC samples processed by the FIR as
determined by the FIR_LEN[1:0] (I/O RAM 0x210C[2:1] control field. Each multiplexer state starts on the
rising edge of CK32, the 32-kHz clock.
It is recommended that MUX_DIV[3:0] (I/O RAM 0x2200[2:0]) be set to zero while changing the ADC
configuration, to minimize system transients that might be caused by momentary shorts between the ADC
inputs, especially when changing the DIFFn_E control bits (I/O RAM 0x210C[5:4]). After the configuration
bits are set, MUX_DIV[3:0] should be set to the required value.
The duration of each time slot in CK32 cycles depends on FIR_LEN[1:0], ADC_DIV and PLL_FAST:
Time_Slot_Duration = (3-2*PLL_FAST)*(FIR_LEN[1:0]+1) * (ADC_DIV+1)
The duration of a multiplexer frame in CK32 cycles is:
MUX_Frame_Duration = 3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV[3:0]
The duration of a multiplexer frame in CK_FIR cycles is:
MUX frame duration (CK_FIR cycles) =
[3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV] * (48+PLL_FAST*102)
The ADC conversion sequence is programmable through the MUXn_SEL control fields (I/O RAM 0x2100
to 0x2105). As stated above, there are up to eleven ADC time slots in the 71M6543, as set by
MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). In the expression MUXn_SEL[3:0] = x, ‘n’ refers to the multiplexer
frame time slot number and ‘x’ refers to the desired ADC input number or ADC handle (i.e., IADC0 to VADC10,
or simply 0 to 10 decimal). Thus, there are a total of 11 valid ADC handles in the 71M6543 devices. For
example, if MUX0_SEL[3:0] = 0, then IADC0, corresponding to the sample from the IADC0-IADC1 input
(configured as a differential input), is positioned in the multiplexer frame during time slot 0. See Table 1 and
Table 2 for the appropriate MUXn_SEL[3:0] settings and other settings applicable to a particular meter
configuration and CE code.
Note that when the remote sensor interface is enabled, the samples corresponding to the remote
sensor currents do not pass through the 71M6543 multiplexer. The sampling of the remote current
sensors occurs in the second half of the multiplexer frame. The VA, VB and VC voltages are assigned
the last three slots in the frame. With this slot assignment for VA, VB and VC, the sampling of the
corresponding remote sensor currents bears a precise timing relationship to their corresponding phase
voltages, and delay compensation is accurately performed (see 2.2.3 Delay Compensation on page 19).
Also when using remote sensors, it is necessary to introduce unused slots to realize the number of
slots specified by the MUX_DIV[3:0] (I/O RAM 0x2100[7:4]) field setting (see Figure 4 and Figure 5). The
MUXn_SEL[3:0] control fields for these unused (“dummy”) slots must be written with a valid ADC handle
(i.e., 0 to 10 decimal) that is not otherwise being used. In this manner, the unused ADC handle, is used
as a “dummy” place holder in the multiplexer frame, and the correct duration multiplexer frame
sequence is generated and also the desired sample rate. The resulting sample data stored in the CE
RAM location corresponding to the “dummy” ADC handle is ignored by the CE code. Meanwhile, the
digital isolation interface takes care of automatically storing the samples for the remote current sensors
in the appropriate CE RAM locations.
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