71M6543F/H and 71M6543G/GH Data Sheet
Table 2. Required CE Code and Settings for CT Sensors
I/O RAM
Mnemonic
FIR_LEN[1:0]
ADC_DIV
PLL_FAST
MUX_DIV[3:0]
MUX0_SEL[3:0]
I/O RAM
Location
210C[2:1]
2200[5]
2200[4]
2100[7:4]
2105[3:0]
I/O RAM Setting
Comments
(Hex)
1
0
1
7
2
288 cycles
Fast
19.66 MHz
See note 1
Slot 0 is IADC2-IADC3
(IA)
MUX1_SEL[3:0]
MUX2_SEL[3:0]
MUX3_SEL[3:0]
MUX4_SEL[3:0]
MUX5_SEL[3:0]
MUX6_SEL[3:0]
Slot 1 is VADC8
(VA)
Slot 2 is IADC4-IADC5
(IB)
Slot 3 is VADC9
(VB)
Slot 4 is IADC6-IADC7
(IC)
Slot 5 is VADC10
(VC)
Slot 6 is IADC0-IADC1
(IN – See note 2)
2105[7:4]
2104[3:0]
2104[7:4]
2103[3:0]
2103[7:4]
2102[3:0]
8
4
9
6
A
0
MUX7_SEL[3:0]
MUX8_SEL[3:0]
MUX9_SEL[3:0]
MUX10_SEL[3:0]
RMT2_E
2102[7:4]
2101[3:0]
2101[7:4]
2100[3:0]
2709[3]
0
0
0
0
0
0
0
1
1
1
1
0
5
Slots not enabled
Local Sensor IADC2-IADC3
Local Sensor IADC4-IADC5
Local Sensor IADC6-IADC7
Differential IADC0-IADC1
Differential IADC2-IADC3
Differential IADC4-IADC5
Differential IADC6-IADC7
IADC0-IADC1 Gain = 1
RMT4_E
RMT6_E
DIFF0_E
DIFF2_E
DIFF4_E
DIFF6_E
PRE_E
EQU[2:0]
2709[4]
2709[5]
210C[4]
210C[5]
210C[6]
210C[7]
2704[5]
2106[7:5]
IA*VA + IB*VB + IC*VC
CE Code
ce43a02
Equation(s)
Current Sensor Type
Applicable Figures
Notes:
5
4 Current Transformers (CTs)
Figure 3, Figure 4 and Figure 32
1. MUX_DIV[3:0] should be set to 0 while writing the other values in this table, and then set to
the indicated value before writing the MUXn_SEL[3:0] fields.
2. IN is the optional Neutral Current
Teridian updates the CE code periodically. Please contact your local Teridian representative to
obtain the latest CE code and the associated settings.
16
© 2008–2011 Teridian Semiconductor Corporation
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