Pin Information
Pin Descriptions
Table 6: Device Bus Interface Pin Assignments (Continued)
Pin Name
I/O
Pin Type
Power
Rail
Description
DEV_AD[15:8]/
DEV_A[14]/
DEV_A[15])
t/s
I/O
CMOS
VDDO_C
Used as DEV_AD[15:8] (device data bus) during the data phase.
Driven by MV78100 on write access, and by the device on read
access.
NOTE: These pins have integrated pullup/pulldown resistors.
See details in Table 22, Reset Configuration, on page 52.
DEV_AD[8] is used as DEV_A[14] (device address bus) during
first ALE cycle (DEV_ALE[1]).
DEV_AD[8] is used as DEV_A[15] (device address bus) during
second ALE cycle (DEV_ALE[0]).
DEV_AD[31:16]
t/s
I/O
CMOS
VDDO_B
Used as DEV_AD[31:16] (device data bus) during the data
phase.
Driven by MV78100 on write access, and by the device on read
access.
NOTE: When using Device Bus as a 8/16b interface,
DEV_AD[23:16] can be used for other functions. See
Section 6, Pin Multiplexing.
These pins have integrated pullup/pulldown resistors.
See details in Table 22, Reset Configuration, on page 52.
DEV_A[2:0]/
DEV_A[5:3]/
DEV_A[18:16]
t/s
I/O
CMOS
VDDO_C
Device Bus Address Bus
Used as DEV_A[2:0] during the data phase.
DEV_A[2:0] is not latched, but connected directly to the device. It
is an incrementing address in case of burst access.
NOTE:
These pins have integrated pullup/pulldown resistors.
See details in Table 22, Reset Configuration, on page 52.
Device Bus Address
Used as DEV_A[5:3] during the first ALE cycle (DEV_ALE[1]).
Device Bus address
Used as DEV_A[18:16] during the second ALE cycle
(DEV_ALE[0]).
DEV_READYn
I
CMOS
CMOS
VDDO_C
VDDO_C
Device READY
Used as cycle extender when interfacing a slow device.
NOTE: When inactive during a device access, access is
extended until DEV_READYn assertion.
This pin has an integrated pulldown resistor.
DEV_BURSTn/
DEV_LASTn
O
Device Burst/Device Last
Copyright © 2008 Marvell
MV-S104552-U0 Rev. D
December 6, 2008, Preliminary
Document Classification: Proprietary Information
Page 27
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
