Pin Information
Pin Descriptions
2.2.3
DDR SDRAM Interface Pin Assignments
Table 5: DDR SDRAM Interface Pin Assignments
Pin Name
I/O
Pin Type
Power
Rail
Description
M_CLKOUT[2:0]
M_CLKOUTn[2:0]
O
SSTL
VDD_M
Three pairs of DRAM differential clocks.
When not using all clock pairs use one of the following strapping
configurations and register setting for the unused pair/s:
•
Leave the unused pair unconnected. In addition, for the
unused pair, set <Clk1Drv> bit[12] or <Clk2Drv> bit[13] to 1
(driven normally), in the DDR Controller Control (Low) (Offset:
0x1404).
•
Connect the unused pair to pull down. In addition, for the
unused pair, set <Clk1Drv> bit[12] or <Clk2Drv> bit[13] to 0
(high-z).
NOTE: M_CLKOUT[0] and M_CLKOUTn[0] cannot be disabled
and is always driven.
M_CKE[3:0]
O
SSTL
VDD_M
Driven by the MV78100 device high to enable DRAM clock.
Driven low when setting the DRAM in self refresh mode.
NOTES:
•
All four CKE pins are driven together (no separate self refresh
per each DRAM bank).
•
When unused can be left unconnected.
M_RASn
M_CASn
O
O
SSTL
SSTL
VDD_M
VDD_M
SDRAM Row Address Select
Asserted to indicate an active ROW address driven on the
SDRAM address lines.
SDRAM Column Address Select
Asserted to indicate an active column address driven on the
SDRAM address lines.
M_WEn
O
O
SSTL
SSTL
VDD_M
VDD_M
SDRAM Write Enable
Asserted to indicate a write command to the SDRAM.
M_A[14:0]
SDRAM Address
Driven during RASn and CASn cycles to generate, together with
the bank address bits, the SDRAM address.
M_BA[2:0]
O
O
SSTL
VDD_M
Driven by the MV78100 device during M_RASn and M_CASn
cycles to select one of the eight DRAM virtual banks.
NOTE: If an SDRAM device does not support the BA[2] pin, leave
the M_BA[2] unconnected.
M_CSn[3:0]
M_DQ[63:0]
SSTL
SSTL
VDD_M
VDD_M
SDRAM Chip Selects
Asserted to select a specific SDRAM bank.
NOTE: When unused can be left unconnected.
t/s
SDRAM Data Bus
I/O
Driven during write to SDRAM.
Driven by SDRAM during reads.
NOTE: When configured to 32-bit mode, M_DQ[63:32] can be left
unconnected.
Copyright © 2008 Marvell
MV-S104552-U0 Rev. D
December 6, 2008, Preliminary
Document Classification: Proprietary Information
Page 23
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
