MV78100
Hardware Specifications
Table 9: Gigabit Ethernet Port Interface Pin Assignments (Continued)
Pin Name
I/O
Pin
Type
Power
Rail
Description
GE0_TXCTL/
GE0_TXEN
t/s
O
CMOS
VDD_GE
RGMII Transmit Control
Transmit control synchronous to the GE0_TXCLKOUT output
rising/falling edge.
GE0_TXCTL is presented on the rising edge of GE0_TXCLKOUT.
A logical derivative of GE0_TXEN and GE0_TxER is presented on
the falling edge of GE0_TXCLKOUT.
NOTE: Internally pulled down to 0x0.
MII Transmit Enable
Indicates that the packet is being transmitted to the PHY. It Is
synchronous to GE0_TXCLK.
GMII Transmit Enable
Indicates that the packet is being transmitted to the PHY.
It Is synchronous to GE0_TXCLKOUT.
GE0_TXERR
t/s
O
CMOS
CMOS
VDDO_D
VDDO_D
MII Transmit Error
It is synchronous to GE0_TXCLK.
NOTE: Multiplexed on MPP.
GMII Transmit Error
It Is synchronous to GE0_TXCLKOUT.
NOTE: Multiplexed on MPP.
GE0_CRS
I
MII Carrier Sense
Indicates that the receive medium is non-idle. In half-duplex mode,
GE0_CRS is also asserted during transmission. GE0_CRS is not
synchronous to any clock.
NOTE: Multiplexed on MPP.
GMII Carrier Sense
NOTE: Multiplexed on MPP.
GE0_RXD[3:0]
I
CMOS
VDD_GE
RGMII Receive Data
Contains the receive data nibble inputs that are synchronous to
GE0_RXCLK input rising/falling edge.
MII Receive Data
Contains the receive data nibble inputs that are synchronous to
GE0_RXCLK input.
GMII Receive Data
Contains the receive data nibble inputs that are synchronous to
GE0_RXCLK input.
GE0_RXD[7:4]
I
CMOS
VDDO_D
GMII Receive Data
Contains the receive data nibble inputs that are synchronous to
GE0_RXCLK input.
NOTE: Multiplexed on MPP.
MV-S104552-U0 Rev. D
Page 30
Copyright © 2008 Marvell
Document Classification: Proprietary Information
December 6, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
