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MV78100-A0-BHO1C100 参数 Datasheet PDF下载

MV78100-A0-BHO1C100图片预览
型号: MV78100-A0-BHO1C100
PDF下载: 下载PDF文件 查看货源
内容描述: 发现™系列的创新CPU系列硬件规格 [Discovery™ Innovation Series CPU Family Hardware Specifications]
分类和应用:
文件页数/大小: 124 页 / 1524 K
品牌: MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
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MV78100  
Hardware Specifications  
2.2.4  
Device Bus Interface Pin Assignments  
If using a 16-bit Device Bus, DEV_AD[23:16] and DEV_WEn[3:2] can be used for pins  
multiplexing (as MPP pins). If using an 8-bit Device Bus also DEV_AD[15:9] and  
DEV_WEn[1] can be used for pins multiplexing (see Section 6, Pin Multiplexing,  
Note  
on page 44 for more details).  
NAND Flash interface signals are multiplexed on the Device Bus interface and on MPP  
pins. Refer to the NAND Flash section in the MV76100, MV78100, and MV78200  
Functional Specifications for more information.  
Table 6: Device Bus Interface Pin Assignments  
Pin Name  
I/O  
Pin Type  
Power  
Rail  
Description  
DEV_CSn[3:0]  
DEV_BootCSn  
O
CMOS  
VDDO_C  
VDDO_C  
VDDO_C  
Device Bus Chip Select corresponds to Bank [3:0].  
NOTE: These pins have internal pullup resistors.  
O
CMOS  
Device Bus Boot Chip Select corresponds to Boot Bank.  
NOTE: This pin has an integrated pullup resistor.  
DEV_OEn/  
DEV_A[15]  
O
CMOS  
Device Bus Output Enable  
NOTE: This pin has an integrated pullup resistor.  
Used as DEV_A[15] (device address bus) during first ALE cycle  
(DEV_ALE[1]).  
DEV_WEn[3:0]/  
DEV_A[16]  
O
O
CMOS  
VDDO_C  
Device Bus Byte Write Enable (bit per byte)  
NOTE: These pins have integrated pullup/pulldown resistors.  
See details in Table 22, Reset Configuration, on page 52.  
DEV_WEn[0] is used as DEV_A[16] (device address bus) during  
first ALE cycle (DEV_ALE[1]).  
DEV_ALE[1:0]  
CMOS  
CMOS  
VDDO_C  
VDDO_C  
Device Bus Address Latch Enable  
NOTE: These pins have integrated pullup/pulldown resistors.  
See details in Table 22, Reset Configuration, on page 52.  
DEV_AD[7:0]/  
DEV_A[13:6]/  
DEV_A[26:19]  
t/s  
I/O  
Used as DEV_AD[7:0] (device data bus) during the data phase.  
Driven by MV78100 on write access, and by the device on read  
access.  
NOTE: These pins have integrated pullup/pulldown resistors.  
See details in Table 22, Reset Configuration, on page 52.  
Used as DEV_A[13:6] (device address bus) during first ALE cycle  
(DEV_ALE[1]).  
Used as DEV_A[26:19] (device address bus) during second ALE  
cycle (DEV_ALE[0]).  
MV-S104552-U0 Rev. D  
Page 26  
Copyright © 2008 Marvell  
Document Classification: Proprietary Information  
December 6, 2008, Preliminary  
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