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MV78100-A0-BHO1C100 参数 Datasheet PDF下载

MV78100-A0-BHO1C100图片预览
型号: MV78100-A0-BHO1C100
PDF下载: 下载PDF文件 查看货源
内容描述: 发现™系列的创新CPU系列硬件规格 [Discovery™ Innovation Series CPU Family Hardware Specifications]
分类和应用:
文件页数/大小: 124 页 / 1524 K
品牌: MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
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MV78100  
Hardware Specifications  
Table 5: DDR SDRAM Interface Pin Assignments (Continued)  
Pin Name  
I/O  
Pin Type  
Power  
Rail  
Description  
M_CB[7:0]  
t/s  
I/O  
SSTL  
VDD_M  
VDD_M  
DRAM ECC  
Driven by the MV78100 during write to SDRAM.  
Driven by SDRAM during reads.  
NOTE: When ECC is unused, leave M_CB[7:0] unconnected.  
M_DQS[8:0],  
M_DQSn[8:0]  
t/s  
I/O  
SSTL  
SSTL  
SDRAM Data Strobe  
Driven by the MV78100 during write to SDRAM.  
Driven by SDRAM during reads.  
NOTES:  
When ECC is unused, leave M_DQS[8] unconnected.  
When configured to 32-bit mode, M_DQS[7:4] and  
M_DQSn[7:4] can be left unconnected.  
M_DM[8:0]  
O
VDD_M  
SDRAM Data Mask  
Asserted by the MV78100 to select the specific bytes out of the  
72-bit data/ECC to be written to the SDRAM.  
NOTES:  
When ECC is unused, leave M_DM[8]/M_DQSn[8]  
unconnected.  
When configured to 32-bit mode, M_DM[7:4] can be left  
unconnected.  
M_ODT[3:0]  
O
SSTL  
VDD_M  
SDRAM On Die Termination Control  
Driven by the MV78100 device high to connect DRAM on die  
termination, and low to disconnect the DRAM termination.  
NOTES:  
For the recommended setting, refer to the MV76100,  
MV78100, and MV78200 Design Guide.  
When unused can be left unconnected.  
M_STARTBURST  
O
I
SSTL  
SSTL  
VDD_M  
VDD_M  
MV78100 indication of starting a burst.  
NOTE: For the exact length calculation for routing and  
termination requirements, see the MV76100, MV78100,  
and MV78200 Design Guide.  
M_START  
BURST_IN  
M_STARTBURST signal routed back to MV78100. Used as a  
reference signal for the incoming read data driven by the  
SDRAM.  
NOTE: For the exact length calculation for routing and  
termination requirements, see the MV76100, MV78100,  
and MV78200 Design Guide.  
M_BB  
I
I
CMOS  
Calib  
VDDO_C  
SDRAM battery backup trigger  
NOTE: This signal is multiplexed on the MPP pins, see Section 6,  
Pin Multiplexing, on page 44.  
M_PCAL  
DRAM interface signals P channel output driver calibration.  
Connect to VSS through a 35–70 Ω resistor.  
NOTE: See the MV76100, MV78100, and MV78200 Design  
Guide for the recommended values of the calibration  
resistors.  
MV-S104552-U0 Rev. D  
Page 24  
Copyright © 2008 Marvell  
Document Classification: Proprietary Information  
December 6, 2008, Preliminary  
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