SXT6051 STM-1/0 SDH Overhead Terminator
Clock Distribution and Reference
Depending on the chip configuration, the source of the Transmit Clock references
Table 7: Operating Mode Vs. Input Clock Source Reference
Transmit
Frame
Parallel Clock
Reference
output
Transmit
Frame
Serial Clock
Reference
output
MSP & TSOH
Bus
Parallel Clock
Reference
output
Telecom Bus
Parallel Clock
Reference
output
VC3/4 &
TPOH Bus
Clock
Reference
output
MHBCLKO
MICLK
MMSPPCKO
MTBCKO
TPOHCK
OPERATING
MODE
CLOCK SOURCE (INPUT PIN)
Repeater
Not used
(tri-state)
DHICLK (1)
DHICLK / 8 (1)
Not used
(tri-state)
Not used
(tri-state)
Serial interface
(51.84 MHz
±20ppm)
(6.48 MHz
±20ppm)
Repeater
DHBCLK (2)
Not used
(tri-state)
DHBCLK (2)
Not used
(tri-state)
Not used
(tri-state)
Parallel interface (6.48/19.44 MHz
± 20ppm)
(6.48/19.44 MHz
±20ppm)
Terminal
Not used
(tri-state)
MHICLK
MHICLK / 8
MHICLK / 8
MHICLK / 8
No Protection
Serial interface
Terminal
(51.84 MHz
±20ppm)
(6.48 MHz
±20ppm)
(6.48 MHz
±20ppm)
(6.48 MHz
±20 ppm)
MHBCLKI
Not used
(tri-state)
MHBCLKI
MHBCLKI
MHBCLKI
(6.48/
19.44MHz
± 20ppm)
No Protection
Parallel interface
(6.48/19.44 MHz
± 20ppm)
(6.48/19.44 MHz
±20ppm)
(6.48/19.44 MHz
±20ppm)
ADM
Not used
(tri-state)
MHICLK
MHICLK / 8
Not used
(tri-state)
MTBCLKI
No Protection
Serial interface
(51.84 MHz
±20ppm)
(6.48 MHz
±20 ppm)
(6.48 MHz
±20 ppm)
40
LevelOne [ LEVEL ONE ]
