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LTC4270CIUKG#PBF 参数 Datasheet PDF下载

LTC4270CIUKG#PBF图片预览
型号: LTC4270CIUKG#PBF
PDF下载: 下载PDF文件 查看货源
内容描述: [LTC4270/LTC4271 - 12-Port PoE/PoE+/LTPoE++ PSE Controller; Package: QFN; Pins: 52; Temperature Range: -40°C to 85°C]
分类和应用: 控制器
文件页数/大小: 32 页 / 335 K
品牌: Linear [ Linear ]
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LTC4270/LTC4271  
APPLICATIONS INFORMATION  
Table 5. Example Current Limit Settings  
INTERNAL REGISTER SETTING (hex)  
The shaded areas in Table 5 indicate settings that may  
require a larger external MOSFET, additional heat sinking,  
or setting t Enable.  
LIM  
I
(mA)  
R
SENSE  
= 0.5Ω  
R
SENSE  
= 0.25Ω  
LIM  
53  
88  
MOSFET Fault Detection  
106  
159  
213  
266  
319  
372  
08  
89  
80  
8A  
09  
8B  
88  
LTC4270/LTC4271 PSE ports are designed to tolerate  
significant levels of abuse, but in extreme cases it is pos-  
sible for the external MOSFET to be damaged. A failed  
MOSFET may short source to drain, which will make the  
port appear to be on when it should be off; this condition  
may also cause the sense resistor to fuse open, turning  
off the port but causing the LTC4270 SENSE pin to rise  
to an abnormally high voltage. A failed MOSFET may also  
short from gate to drain, causing the LTC4270 GATE pin  
to rise to an abnormally high voltage. The LTC4270 OUT,  
SENSE and GATE pins are designed to tolerate up to 80V  
faults without damage.  
08  
89  
425  
478  
00  
8E  
92  
CB  
10  
D2  
40  
4A  
50  
5A  
60  
52  
80  
531  
8A  
584  
638  
90  
9A  
C0  
CA  
D0  
DA  
E0  
49  
40  
4A  
50  
5A  
60  
52  
744  
850  
If the LTC4270/LTC4271 sees any of these conditions for  
more than 180ꢀs, it disables all port functionality, reduces  
the gate drive pull-down current for the port and reports  
a FET Bad fault. This is typically a permanent fault, but  
the host can attempt to recover by resetting the port, or  
by resetting the entire chip if a port reset fails to clear the  
fault. If the MOSFET is in fact bad, the fault will quickly  
return, and the port will disable itself again. The remaining  
ports of the LTC4270/LTC4271 are unaffected.  
956  
1063  
1169  
1275  
1488  
1700  
1913  
2125  
2338  
2550  
2975  
An open or missing MOSFET will not trigger a FET Bad  
fault, but will cause a t  
fault if the LTC4270/LTC4271  
START  
attempts to turn on the port.  
I
Foldback  
LIM  
Port Current Readback  
TheLTC4270/LTC4271featuresatwo-stagefoldbackcircuit  
that reduces the port current if the port voltage falls below  
the normal operating voltage. This keeps MOSFET power  
dissipation at safe levels for typical 802.3af MOSFETs,  
even at extended 802.3at power levels. Current limit and  
foldback behavior are programmable on a per-port basis.  
The LTC4270/LTC4271 measures the current at each port  
with an internal A/D converter. Port data is only valid when  
the port power is on and reads zero at all other times. The  
converter has two modes:  
• 100ms mode: Samples are taken continuously and the  
measured value is updated every 100ms  
Table 5 gives examples of recommended I  
settings.  
register  
LIM  
• 1s mode: Samples are taken continuously; a moving 1  
second average is updated every 100ms  
The LTC4270/LTC4271 will support current levels well  
beyond the maximum values in the 802.3at specification.  
42701f  
23  
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