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GM72V66841CT 参数 Datasheet PDF下载

GM72V66841CT图片预览
型号: GM72V66841CT
PDF下载: 下载PDF文件 查看货源
内容描述: 2,097,152字×8位×4银行同步动态RAM [2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM]
分类和应用:
文件页数/大小: 57 页 / 591 K
品牌: LG [ LG SEMICON CO.,LTD. ]
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LG Semicon  
GM72V66841CT/CLT  
Auto-refresh command[REF]: When this  
command is input from the IDLE state, the  
synchronous DRAM starts auto-refresh  
Self-refresh exit[SELFX]: When this command  
is executed during self-refresh mode, the  
synchronous DRAM can exit from self-refresh  
mode. After exiting from self-refresh mode, the  
synchronous DRAM enters the IDLE state.  
operation. (The auto-refresh is the same as the  
CBR refresh of conventional DRAMs.) During  
the auto-refresh operation, refresh address and  
bank select address are generated inside the  
synchronous DRAM. For every auto-refresh  
cycle, the internal address counter is updated.  
Accordingly, 4,096 times are required to refresh  
the entire memory. Before executing the auto-  
refresh command, all the banks must be in the  
IDLE state. In addition, since the Precharge for  
all banks is automatically performed after auto-  
refresh, no Precharge command is required after  
auto-refresh.  
Power down mode entry: When this command  
is executed during the IDLE state, the  
synchronous DRAM enters Power down mode.  
In Power down mode, Power consumption is  
suppressed by cutting off the initial input circuit.  
Power down exit: When this command is  
executed at the Power down mode, the  
synchronous DRAM can exit from Power down  
mode. After exiting from Power down mode, the  
synchronous DRAM enters the IDLE state.  
Self-refresh entry[SELF]: When this command  
is input during the IDLE state, the synchronous  
DRAM starts self-refresh operation. After the  
execution of this command, self-refresh  
continues while CKE is Low. Since self-refresh  
is performed internally and automatically,  
external refresh operations are unnecessary.  
Function Truth Table  
The following table shows the operations that are performed when each command is issued in each  
mode of the synchronous DRAM.  
Current  
state  
CS RAS CAS WE  
Address  
Command  
DESL  
Operation  
Precharge  
H
L
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
Enter IDLE after tRP  
Enter IDLE after tRP  
NOP  
NOP  
BST  
H
L
BA, CA, A10 READ/READ A ILLEGAL  
BA, CA, A10 WRIT/WRIT A ILLEGAL  
L
H
H
H
L
BA, RA  
ACTV  
ILLEGAL  
NOP  
L
BA, A10  
PRE, PALL  
8
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