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GM72V66841CT 参数 Datasheet PDF下载

GM72V66841CT图片预览
型号: GM72V66841CT
PDF下载: 下载PDF文件 查看货源
内容描述: 2,097,152字×8位×4银行同步动态RAM [2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM]
分类和应用:
文件页数/大小: 57 页 / 591 K
品牌: LG [ LG SEMICON CO.,LTD. ]
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LG Semicon  
GM72V66841CT/CLT  
Function Truth Table (Continued)  
Current  
state  
CS RAS CAS WE  
Address  
Command  
DESL  
Operation  
Refresh  
(auto-refresh)  
H
L
L
L
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
Enter IDLE after tRC  
Enter IDLE after tRC  
Enter IDLE after tRC  
NOP  
BST  
H
L
BA, CA, A10 READ/READ A ILLEGAL  
BA, CA, A10 WRIT/WRIT A ILLEGAL  
L
ILLEGAL  
H
H
L
H
L
BA, RA  
BA, A10  
X
ACTV  
L
PRE, PALL  
REF, SELF  
MRS  
ILLEGAL  
ILLEGAL  
ILLEGAL  
L
H
L
L
L
MODE  
* Notes : 1. H: VIH, L: VIL, X: VIH or VIL.  
The other combinations are inhibit.  
2. An interval of tRWL is required between the final valid data input and the Precharge command.  
3. If tRRD is not satisfied, this operation is illegal.  
4. BA:Bank Address, RA:Row Address, CA:Column Address  
From [ROW ACTIVE]  
From [Precharge]  
To [DESL], [NOP] or [BST]: These  
commands result in no operation.  
To [DESL], [NOP] or [BST]: When these  
commands are executed, the synchronous  
DRAM enters the IDLE state after tRP has  
elapsed from the completion of Precharge  
To [READ], [READ A]: A read operation  
starts. (However, an interval of tRCD is  
required.)  
From [IDLE]  
To [WRIT], [WRIT A]: A write operation  
starts. (However, an interval of tRCD is  
required.)  
To [DESL], [NOP], [BST], [PRE] or  
[PALL]: These commands result in no  
operation.  
To [ACTV]: The bank specified by the  
address pins and the ROW address is  
activated.  
To [ACTV]: This command makes the  
other bank active. (However, an interval of  
t
RRD is required.) Attempting to make the  
currently active bank active results in an  
illegal command.  
To [REF], [SELF]: The synchronous  
DRAM enters refresh mode (auto-refresh or  
self-refresh).  
To [PRE], [PALL]: These commands set  
the synchronous DRAM to Precharge  
mode. (However, an interval of tRAS is  
required.)  
To [MRS]: The synchronous DRAM enters  
the mode register set cycle.  
12