Pinout Information
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Pin Information Summary (Cont.)
LFECP/EC15
LFECP20/EC20
LFECP/EC33
Pin Type
Single Ended User I/O
Differential Pair User I/O
256-fpBGA
484-fpBGA
484-fpBGA
672-fpBGA
484-fpBGA
672-fpBGA
195
97
352
176
13
360
180
13
400
200
13
360
180
13
496
248
13
Dedicated
Muxed
13
Configuration
56
56
56
56
56
56
TAP
5
5
5
5
5
5
Dedicated (total without supplies)
208
10
373
20
373
20
509
32
373
16
509
28
V
V
V
CC
2
12
12
20
12
20
CCAUX
CCPLL
0
0
0
0
4
4
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
2
4
4
6
4
6
2
4
4
6
4
6
2
4
4
6
4
6
2
4
4
6
4
6
V
CCIO
2
4
4
6
4
6
2
4
4
6
4
6
2
4
4
6
4
6
2
4
4
6
4
6
GND, GND0-GND7
NC
20
44
44
63
44
63
0
11
3
96
3
0
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
32/16
18/9
16/8
32/16
17/8
32/16
32/16
16/8
1
48/24
48/24
40/20
40/20
48/24
48/24
40/20
40/20
1
48/24
48/24
40/20
44/22
48/24
48/24
44/22
40/20
1
64/32
48/24
40/20
48/24
48/24
64/32
48/24
40/20
1
48/24
48/24
40/20
44/22
48/24
48/24
44/22
40/20
1
64/32
64/32
56/28
64/32
64/32
64/32
64/32
56/28
1
Single Ended/
Differential I/O
Pair per Bank
V
CCJ
Note: During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not
bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration.
4-5
LATTICE [ LATTICE SEMICONDUCTOR ]
