Pinout Information
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
PICs Associated
with DQS Strobe
DDR Strobe (DQS) and
Data (DQ) Pins
PIO Within PIC
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
DQ
DQ
P[Edge] [n-4]
DQ
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
DQ
DQ
DQ
DQ
DQ
[Edge]DQSn
DQ
DQ
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
DQ
DQ
DQ
DQ
DQ
Notes:
1. “n” is a Row/Column PIC number
2. The DDR interface is designed for memories that support one DQS strobe per eight bits of
data. In some packages, all the potential DDR data (DQ) pins may not be available.
3. PIC numbering definitions are provided in the “Signal Names” column of the Signal Descrip-
tions table.
4-3
LATTICE [ LATTICE SEMICONDUCTOR ]
