Pinout Information
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Pin Information Summary
LFEC1
LFEC3
LFECP6/EC6
LFECP/EC10
100- 144- 208- 100- 144- 208- 256- 144- 208- 256- 484- 208- 256- 484-
TQFP TQFP PQFP TQFP TQFP PQFP fpBGA TQFP PQFP fpBGA fpBGA PQFP fpBGA fpBGA
Pin Type
Single Ended User
I/O
67
29
97
46
112
56
67
29
97
46
145
72
160
80
97
46
147
72
195
97
224
112
147
72
195
97
288
144
Differential Pair User
I/O
Dedicated 13
13
48
5
13
48
5
13
48
5
13
48
5
13
48
5
13
48
5
13
48
5
13
48
5
13
48
5
13
48
5
13
56
5
13
56
5
13
56
5
Configu-
ration
Muxed
48
5
TAP
Dedicated (total
without supplies)
80
110
160
80
110
160
208
110
160
208
373
160
208
373
V
V
V
2
2
0
1
1
1
1
1
1
1
1
8
0
3
2
3
2
2
4
0
1
1
2
1
1
1
1
2
8
0
3
4
3
4
10
4
4
2
4
4
10
2
20
12
0
6
4
10
2
20
12
0
CC
CCAUX
CCPLL
0
0
0
0
0
0
0
0
0
0
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
2
2
2
3
2
2
3
2
4
3
2
4
2
2
2
2
2
2
2
2
4
2
2
4
1
1
2
2
2
1
2
2
4
2
2
4
2
2
2
2
2
2
2
2
4
2
2
4
V
CCIO
2
2
2
2
2
2
2
2
4
2
2
4
2
2
2
2
2
2
3
2
4
3
2
4
2
2
2
2
2
2
2
2
4
2
2
4
1
1
2
2
2
1
2
2
4
2
2
4
GND, GND0-GND7
13
2
13
51
13
2
16
9
20
35
14
0
18
4
20
0
44
139
20
0
20
0
44
75
NC
Bank 0
Bank 1
11/5 14/7 16/8 11/5 14/7 26/13 32/16 14/7 26/13 32/16 32/16 26/13 32/16 48/24
11/5 13/6 16/8 11/5 13/6 16/8 16/8 13/6 17/8 18/9 32/16 17/8 18/9 32/16
Single
Ended/
Differen-
tial I/O
Pair per
Bank
Bank 2
3/1
8/4 13/6 16/8
12/4 14/6 16/8 12/4 14/6 16/8 16/8 14/6 17/8 17/8 32/16 17/8 17/8 32/16
8/4
8/4
3/1
8/4
14/7 16/8
8/4
14/7 16/8 16/8 14/7 16/8 32/16
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
8/4 13/6 16/8 16/8 13/6 16/8 32/16 32/16 16/8 32/16 32/16
9/4 13/6 16/8
5/2 14/7 16/8
9/4 13/6 26/13 32/16 13/6 26/13 32/16 32/16 26/13 32/16 48/24
5/2 14/7 16/8 16/8 14/7 16/8 32/16 32/16 16/8 32/16 32/16
8/4
1
8/4
1
8/4
1
8/4
1
8/4
1
15/7 16/8
8/4
1
15/7 16/8 16/8 15/7 16/8 32/16
V
1
1
1
1
1
1
1
1
CCJ
Note: During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not
bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration.
4-4
LATTICE [ LATTICE SEMICONDUCTOR ]
