LatticeECP/EC Family Data Sheet
Pinout Information
November 2007
Data Sheet
Signal Descriptions
Signal Name
I/O
Description
General Purpose
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify
Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
[A/B] indicates the PIO within the PIC to which the pad is connected.
P[Edge] [Row/Column Number*]_[A/B]
I/O
Some of these user-programmable pins are shared with special function
pins. These pin when not used as special purpose pins can be programmed
as I/Os for user logic.
During configuration the user-programmable I/Os are tri-stated with an inter-
nal pull-up resistor enabled. If any pin is not used (or not bonded to a pack-
age pin), it is also tri-stated with an internal pull-up resistor enabled after
configuration.
GSRN
NC
I
Global RESET signal (active low). Any I/O pin can be GSRN.
No connect.
—
—
—
GND
Ground. Dedicated pins.
V
V
V
V
Power supply pins for core logic. Dedicated pins.
CC
Auxiliary power supply pin. It powers all the differential and referenced input
buffers. Dedicated pins.
—
—
—
CCAUX
CCIOx
Power supply pins for I/O bank x. Dedicated pins.
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
V
REF1_x, REF2_x
assigned as V
inputs. When not used, they may be used as I/O pins.
REF
XRES
—
—
10K ohm +/-1% resistor must be connected between this pad and ground.
Power supply pin for PLL. Applicable to ECP/EC33 device.
V
CCPLL
PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
Reference clock (PLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
[LOC][num]_PLL[T, C]_IN_A
[LOC][num]_PLL[T, C]_FB_A
PCLK[T, C]_[n:0]_[3:0]
I
I
I
I
Optional feedback (PLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Primary Clock pads, T = true and C = complement, n per side, indexed by
bank and 0,1,2,3 within bank.
DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball
function number. Any pad can be configured to be output.
[LOC]DQS[num]
Test and Programming (Dedicated pins)
Test Mode Select input, used to control the 1149.1 state machine. Pull-up is
enabled during configuration.
TMS
I
I
Test Clock input pin, used to clock the 1149.1 state machine. No pull-up
enabled.
TCK
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