DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LatticeECP/EC Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
-5
-4
-3
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
Clock Enable Setup Time to EBR Output
Register
t
t
t
0.18
—
—
0.21
-0.17
—
—
—
0.25
-0.20
—
—
—
ns
ns
ns
SUCE_EBR
Clock Enable Hold Time to EBR Output Register -0.14
HCE_EBR
Reset To Output Delay Time from EBR Output
Register
—
1.47
1.76
2.05
RSTO_EBR
PLL Parameters
t
Reset Recovery to Rising Clock
Reset Signal Setup Time
1.00
1.00
—
—
1.00
1.00
—
—
1.00
1.00
—
—
ns
ns
RSTREC
t
RSTSU
DSP Block Timing2, 3
t
t
t
t
t
t
t
t
t
t
t
Input Register Setup Time
-0.38
0.71
3.31
0.71
5.54
0.71
—
—
—
-0.30
0.86
3.98
0.86
6.64
0.86
—
—
—
-0.23
1.00
4.64
1.00
7.75
1.00
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SUI_DSP
HI_DSP
Input Register Hold Time
Pipeline Register Setup Time
Pipeline Register Hold Time
—
—
—
SUP_DSP
HP_DSP
SUO_DSP
—
—
—
4
Output Register Setup Time
—
—
—
4
Output Register Hold Time
—
—
—
HO_DSP
4
Input Register Clock to Output Time
Pipeline Register Clock to Output Time
Output Register Clock to Output Time
AdSub Input Register Setup Time
AdSub Input Register Hold Time
7.50
4.66
1.47
—
9.00
5.60
1.77
—
10.50
6.53
2.06
—
COI_DSP
4
—
—
—
COP_DSP
COO_DSP
SUADSUB
HADSUB
—
—
—
-0.38
0.71
-0.30
0.86
-0.23
1.00
—
—
—
1. Internal parameters are characterized but not tested on every device.
2. These parameters apply to LatticeECP devices only.
3. DSP Block is configured in Multiply Add/Sub 18 x 18 Mode.
4. These parameters include the Adder Subtractor block in the path.
Timing v.G 0.30
3-17
LATTICE [ LATTICE SEMICONDUCTOR ]
